Method for arranging logical cells in a semiconductor integrated circuit

A method for arranging a group of logical cells of a semiconductor device having a plurality of layers therein, through which a signal is transmitted from an input terminal to an output terminal on condition that the signal is transmitted within a predetermined delay time which is a design constraint for an allowable wiring delay time determined according to an analysis of a delay time, comprising the computer implemented steps of:

• determining a plurality of equipotential nets of the logical cells, wherein
• (1) the logical cells in each of said plurality of equipotential nets are maintained at an equal potential, and
• (2) the potential of one of said equipotential nets differing from the potential of the other equipotential nets;
• determining signal lines interconnecting the logical cells of each of the equipotential nets;
• defining a critical path including signal lines of each of the equipotential nets;
• classifying the logical cells disposed within the equipotential nets as path core cells and classifying the other logical cells as path branch cells,
• (1) the signal lines connecting the path core cells forming a main signal route of the critical path through which the input terminal is connected with the output terminal,
• (2) an arrangement of the path core cells determining the physical topology of the critical path, and
• (3) an arrangement of the path branch cells being determined by the size of the equipotential nets with respect to the path core cells;
• positioning the path core cells within the semiconductor device so as to shorten the length of the main signal route;
• and
• positioning the path branch cells within the semiconductor device so as to shorten a distance between the main signal route and the path branch cell for each equipotential net so that the delay time of the critical path formed by the positioned path core cells and the positioned path branch cells is within the predetermined delay time;
• wherein the critical path is defined to be a signal route having a design constraint.