Process for forming arrayed field effect transistors highly integrated on substrate

A method for forming an array of floating gate field effect transistors on a semiconductive substrate comprising the steps of:

• providing a multi-layered structure on said substrate with two conductive layers insulatively stacked by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from said substrate, the second or outer conductive layer being covered with a second insulative layer;
• etching said second insulative layer to define therein a first array of etched layer portions;
• forming insulative thin film layers on both side walls of said etched layer portions;
• depositing a radiation-sensitive resist material on the top surface of the resultant structure;
• etching said resist material so that said etched layer portions with said thin film layers are partially exposed;
• removing said thin film layers to thereby define a second array of layer portions each of which is positioned between two neighboring ones of said first array of layer portions;
• etching said multi-layered structure with the first and second layer portions serving as a mask to thereby form an array of pairs of insulated gate electrodes above said substrate;
• and
• doping semiconductor impurity into said substrate with said plurality of insulated gate electrodes serving as a mask to thereby form impurity-doped regions in said substrate.

A method for forming an array of field effect transistors on a semiconductive substrate comprising the steps of:

• providing a multi-layered structure on said substrate with two conductive layers insulatively stacked by an intermediate insulative layer, the first or inner conductive layer being insulated from said substrate by a first insulative layer, the second or outer conductive layer being covered with a second insulative layer;
• etching said second insulative layer to define therein a first array of etched layer portions;
• forming insulative thin film layers on both side walls of said etched layer portions;
• depositing a radiation-sensitive resist material on the top surface of the resultant structure;
• etching said resist material so that said etched layer portions with said thin film layers are partially exposed;
• removing said thin film layers to thereby define a second array of said etched layer portions each of which is positioned between two neighboring ones of said first array of layer portions;
• etching said multi-layered structure with the first and second array of etched layer portions serving as a mask to thereby form an array of a plurality of pairs of insulated gate electrodes above said substrate;
• and completing formation of said array of field effect transistors without the formation of impurity-doped semiconductor regions in said substrate.

A method for forming an array of field effect transistors on a semiconductor substrate, comprising the steps of:

• forming said semiconductor substrate;
• forming a first insulating layer on said substrate;
• forming a first conductive layer on said first insulating layer;
• forming a second insulating layer on said first conductive layer;
• forming a second conductive layer on said second insulating layer;
• forming a third insulating layer on said second conductive layer;
• etching said third insulating layer to form a first array of etched layer portions;
• forming insulative thin film layers on opposite side portions of said etched layer portions;
• depositing a radiation-sensitive resist material on the top surface of the resulting structure;
• etching said resist material so that said etched layer portions with said thin film layers are partially exposed;
• removing said thin film layers to thereby define a second array of etched layer portions each of which is positioned between two adjacent portions of said first array of etched layer portions;
• etching said multi-layered structure with said first and second arrays of etched layer portions serving as a mask to thereby form an array of a plurality of pairs of insulated gate electrodes above said substrate;
• and
• completing formation of said array of field effect transistors without the formation of impurity-doped semiconductor regions in said substrate.