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US 5,396,456 AGranted
Fully used tub DRAM cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsH. T. Liu, J. H. Lee
Life of this patent
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Abstract
A method is described for forming a dynamic random access memory cell capacitor in which a polysilicon spacer is formed on top of the bottom polysilicon electrode to construct a tub shape and a wet dip is used to remove silicon oxide from cavities under the bottom polysilicon electrode, increasing the overlap with the top polysilicon electrode and thus increasing the surface area of the capacitor without increasing the area on the substrate occupied by the capacitor.
Claims5
A dynamic random access memory having a high capacitance capacitor comprising:
- field oxide areas on the surface of a semiconductor substrate which surround device areas for fabrication of field effect devices, gate dielectric and electrode structures on said substrate in said device areas;
- an interconnecting line composed of polysilicon layer over said field oxide areas;
- source/drain structures within said device areas of said semiconductor substrate associated with said gate structures;
- and
- said capacitor structure including:
- a bottom electrode formed by the central portion of a second polysilicon layer which electrically contacts said source/drain structures;
- a storage node having a tub shape formed by two outer portions of said second polysilicon layer having upper and lower surfaces wherein said outer portions extend outwardly and upwardly in opposite directions from said central portion and wherein the upper surfaces of said outer portions form a bottom to said tub shape and wherein vertical portions of a third polysilicon layer having a spacer shape and extending upwardly from the upper surfaces of the ends of said outer portions of said second polysilicon layer form sidewalls to said tub shape;
- a capacitor dielectric layer overlying the upper and lower surfaces of said storage node;
- and
- a top plate electrode overlying said capacitor dielectric layer on both the upper and lower surfaces of said storage node to complete said capacitor.
7 more elements
Dependencies are inferred from the claim text.