DRAM device having cells staggered along adjacent rows and sources and drains aligned in a column direction

A dynamic random access memory device comprising:

• a sense amplifier;
• a bit line connected to said sense amplifier;
• a first group of dynamic memory cells periodically spaced apart by a predetermined spacing along a first row and connected to said bit line;
• and
• a second group of dynamic memory cells periodically spaced apart by said predetermined spacing along a second row which is substantially parallel to said first row and which is spaced from said first row by a predetermined pitch, said second group of dynamic memory cells being connected to said bit line, said first and second groups of dynamic memory cells being arranged side by side and adjacently to each other, and said first and second groups of dynamic memory cells being in staggered relationship to each other in the row direction;
• said bit line extending in a zigzag manner to alternately connect ones of said first and second groups of dynamic memory cells;
• said bit line crossing only a single word line between each pair of connected memory cells;
• said device being arranged as an open bit line system;
• said predetermined spacing comprises a memory cell pitch;
• and said first and second groups of dynamic memory cells are staggered apart relative to each other in a column direction such that they are shifted from adjacent ones in the other one of said first and second groups of dynamic memory cells by a half of the memory cell pitch;
• and wherein
• each of said dynamic memory cells comprises a capacitor and a transfer gate transistor having a gate electrode and first and second regions as source and drain regions;
• said bit line is connected to the first region through a first contact hole formed in a first insulating layer which covers the gate electrode;
• each said capacitor has a first electrode, connected to the second region through a second contact hole formed in the first insulating layer, and a second electrode formed over the first electrode via a second insulating layer;
• and
• the first contact hole corresponds to a first memory cell of the first group of memory cells and the second contact hole corresponds to a second memory cell of the second group of memory cells, which second memory cell is adjacent to the first memory cell in the column direction.