US 5,396,087 A · Insulated gate bipolar transistor with reduced susceptibility to parasitic latch-up

Abstract

A latch-up free insulated gate transistor includes an anode region electrically connected to an anode contact, a first base region on the anode region, a second base region on the first base region, connected to a cathode contact, an insulating region on the second base region and a field effect transistor on the insulating region, electrically connected between the cathode contact and the first base region. The field effect transistor provides an electrical connection between the first base region and the cathode contact in response to a turn-on bias signal. The insulating region prevents electrical conduction between the second base region and the field effect transistor and, in particular, suppresses minority carrier injection from the second base region to the source of the field effect transistor which is electrically connected to the cathode contact. The prevention of minority carrier injection reduces the likelihood of parasitic latch-up by cutting-off the regenerative P-N-P-N path that would otherwise exist between the anode and cathode. The insulating region is selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4 and is preferably formed using SIMOX processing techniques.

Claims19

Dependent claims

A gate-controlled bipolar transistor, extending vertically in a semiconductor substrate between first and second opposing faces, comprising:

an anode region adjacent said first face;
a first base region of a first conductivity type on said anode region and forming a P-N junction therewith;
a second base region of a second conductivity type on said first base region and extending to said second face, said second base region forming a P-N junction with said first base region;
a cathode contact on said second face, electrically contacting said second base region and forming a first ohmic contact therewith;
a field effect transistor extending laterally in said substrate for electrically connecting said cathode contact and said first base region in response to a turn-on bias signal, said field effect transistor having a source region of said first conductivity type in said substrate, electrically contacting said cathode contact and forming a second ohmic contact therewith, and having an active region of said second conductivity type in said substrate;
and
an insulating region in said substrate, said insulating region extending to said second face and extending between said first ohmic contact and said second ohmic contact to thereby prevent electrical conduction from occurring in the semiconductor substrate, between said source region and said second base region.

4 more elements

An insulated gate bipolar transistor comprising:

a semiconductor substrate having a face;
an anode region in said substrate;
a first base region of a first conductivity type on said anode region extending to said face;
a second base region of a second conductivity type on said first base region, extending to said face;
a third base region of said second conductivity type adjacent said second base region, extending to said face and separated from said second base region by said first base region;
a cathode contact on said face, electrically connected to said second and said third base regions;
a first insulating region on said second base region, extending from said cathode contact to said first base region;
a second insulating region on said third base region, extending from said cathode contact to said first base region;
a first field effect transistor, having an active region of said second conductivity type on said first insulating region, extending from said cathode contact onto said first insulating region and to said first base region;
and
a second field effect transistor, having an active region of said second conductivity type on said second insulating region, extending from said cathode contact onto said second insulating region and to said first base region
wherein said first insulating region electrically insulates said active region of said first field effect transistor from said second base region and wherein said second insulating region electrically insulates said active region of said second field effect transistor from said third base region.

9 more elements

An insulated gate bipolar transistor comprising:

a semiconductor substrate having first and second opposing faces;
an anode region of a second conductivity type in said substrate, at the first face;
a first base region of a first conductivity type in said substrate, extending between said anode region and the second face, said first base region forming a P-N junction with said anode region;
a cathode contact on the second face;
and
a first insulated gate bipolar transistor cell in said substrate, said first cell comprising:
a second base region of said second conductivity type in said first base region, said second base region extending to the second face and ohmically contacting said cathode contact;
a first field effect transistor at the second face for providing an electrical connection between said cathode contact and said first base region in response to a turn-on gate bias signal, said first field effect transistor having a first active region of said second conductivity type which extends adjacent said second base region, and a first source region of said first conductivity type which extends adjacent said second base region and ohmically contacts said cathode contact at the second face;
and
a first electrical insulating region in said substrate, extending from said first base region to the second face, said first insulating region formed adjacent to said first source region in said substrate to thereby prevent minority carrier injection between adjacent portions of said first source region and said second base region.

7 more elements

Dependencies are inferred from the claim text.

Insulated gate bipolar transistor with reduced susceptibility to parasitic latch-up

Life of this patent

Insulated gate bipolar transistor with reduced susceptibility to parasitic latch-up

Life of this patent

Abstract

Claims19