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US 5,395,787 AGranted
Method of manufacturing shallow junction field effect transistor
AssigneeAT&T Corp.
InventorsKuo-Hua Lee, Chun-Ting Liu, Ruichen Liu
Life of this patent
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Abstract
Shallow junctions n- and p-channel field effect transistors are formed with a single ion implant into a conformal tungsten silicide layer. Although phosphorous and boron are implanted into the same silicide regions, the phosphorous prevents the boron from outdiffusing.
Claims6
A method of making an integrated circuit comprising at least one n-channel field effect transistor and at least one p-channel transistor comprising the steps of:
- forming regions of first and second conductivity types in a substrate;
- fabricating gate structures of at least one first and at least one second field effect transistors;
- at least one of said at least one first and at least one of said at least one second field effect transistors being in said regions of first and second conductivity types, respectively;
- forming a dopant implant layer on said regions of first and second conductivity types;
- blanket implanting a first dopant having said a first conductivity type in said dopant implant layer on the said regions of first and second conductivity types;
- masking said regions of said second conductivity type;
- blanket implanting a second dopant having said a second conductivity type in the unmasked portion of the dopant implant layer;
- and
- heating the resultant structure to cause said dopants to diffuse from said dopant implant layer and form source/drain regions of said first and said second field effect transistors.
6 more elements
Dependencies are inferred from the claim text.