US 5,395,782 A · Process for fabricating a semiconductor integrated circuit

Abstract

A LOCOS film is formed on the surface of an epitaxial layer. A gate electrode is formed on the epitaxial layer. At the same time that the gate electrode is formed, a lower electrode is formed on the LOCOS film. A diffusion region is formed on each element and then covered with a BPSG film. A contact hole and capacitor exposure are formed in a capacitor element simultaneously. A film of SiN is deposited in layers over the capacitor exposure. The film of SiN covers undesired areas about the capacitor exposure. Excess SiN film outside the desired area over the capacitor exposure is removed by masking and etching to leave the remaining film area over the capacitor exposure to serve as a capacitor dielectric film. Finally, an Al upper electrode is formed over the SiN film to serve as electrode wiring. The process reduces the series resistance of the capacitor element, thereby reducing power required for charging the dielectric, and speeding the charging process. The low resistance eliminates parasitic leakage currents and the formation of parasitic capacitances.

Claims8

Dependent claims

A process for fabricating a semiconductor integrated circuit, comprising:

forming an oxide film area on a semiconductor substrate by local oxidation of silicon;
forming a first oxide film on at least first, second, and third elements of said substrate;
forming a gate electrode on said first oxide film above said first element;
forming a lower electrode on said first oxide film above said second element;
coating a second oxide film on said gate electrode and said lower electrode;
forming simultaneously at least three contact holes to expose a surface of a diffusion region of said first and second elements and a surface of said lower electrode and an opening to expose a substantial part of a surface of said lower electrode;
forming a dielectric film on the resulting surface of said circuit;
coating a resist pattern over said opening of said lower electrode;
removing said dielectric film from said at least three contact holes;
coating an electrode material on the resulting surface of said circuit;
forming an upper electrode upon a portion of said dielectric film;
forming a first electrode contacting said lower electrode through said contact hole which exposes the surface of said lower electrode;
and
forming a set of electrodes contacting each of said diffusion regions.

11 more elements

Dependencies are inferred from the claim text.

Process for fabricating a semiconductor integrated circuit

Life of this patent

Process for fabricating a semiconductor integrated circuit

Life of this patent

Abstract

Claims8