US 5,395,778 AGranted

Method of manufacturing an integrated circuit having a memory element

AssigneeU.S. Philips Corporation

InventorAndrew J. Walker

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Abstract

If the process were to be changed for optimizing the injection of hot electrons into the channel of the memory transistor in the manufacture of an integrated circuit having an embedded EPROM, this could lead to degradation of the transistors in the logic, in particular in the case of channel lengths below 1 .mu.m. To prevent this, a process is presented by which the non-volatile memory is optimized without the properties of the logic being affected. For this purpose, a first series of steps is performed in which first the floating gate is defined, followed by the source/drain implantation and a side-wall oxidation for obtaining an oxide spacer on the sides of the floating gate. During these steps, the region of the logic to be formed is uniformly protected against implantation and oxidation by the same poly layer from which the floating gate is made. Then, in a second series of steps, the usual CMOS process is carried out whereby first the gates of the transistors are formed, followed by the necessary source/drain implantations.

Claims12

Dependent claims

A method of manufacturing an integrated circuit comprising a semiconductor body which is provided at a surface with a field effect transistor with insulated gate electrode and with a non-volatile memory element with a floating gate situated between a control electrode and a channel region which is situated in the semiconductor body and extends in the semiconductor body between a source and a drain zone, by which method a first and a second active region of a first conductivity type adjoining the surface are defined in the semiconductor body for the transistor and for the memory element, respectively, and the surface is coated with an insulating layer forming a gate dielectric at least at the area of the first and the second active region, on which insulating layer a silicon layer is provided from which the gate electrode of the transistor and at least the floating gate of the memory element are formed, characterized in that in a first series of process steps first the floating gate of the memory element is formed from the silicon layer by masked etching while the active region of the transistor remains covered by the silicon layer, after which the source and drain zones of the second conductivity type of the memory element are provided and the floating gate is provided with an oxide layer at least at its edges by means of an oxidation step, which oxide layer will be called spacer hereinafter, and in that in a subsequent series of steps the insulated gate electrode of the transistor is formed from the silicon layer above the other active region by masked etching, and source and drain zones of the second conductivity type of the transistor are provided in the semiconductor body by means of doping.

Dependencies are inferred from the claim text.