Method of producing VDMOS transistors
AssigneeUnited Microelectronics Corp.
InventorSheng-Hsing Yang
Life of this patent
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Abstract
A method of producing reduced-size VDMOS transistors having reduced leakage and a reduced propensity to latch-up. These advantages are attained by reducing the vertical projective area of the source electrodes of the VDMOS transistors. This is done by forming first trenches which are sufficiently deep to reach an epitaxial layer on a substrate of the VDMOS transistors before second trenches are formed.
Claims7
A method of forming VDMOS transistors on a substrate of a first conductivity type having a first conductivity type epitaxial layer, said substrate being a drain electrode of said VDMOS transistors, comprises the following steps:
- (a) forming field oxide on said first conductivity type epitaxial layer to define active regions of said VDMOS transistors;
- (b) forming gates of said VDMOS transistors at predetermined locations on the active regions;
- (c) implanting and diffusing impurities of the first conductivity type into said first conductivity type epitaxial layer to form first conductivity type regions;
- (d) forming first trenches in the first conductivity type regions to define residual portions of the first conductivity type regions adjacent said gates as source regions of said VDMOS transistors;
- (e) forming additional trenches in the first trenches, each of the second trenches having at least two planes;
- (f) implanting impurities of a second conductivity type into the second trenches to form second conductivity type regions, the second conductivity type regions enclosing the source regions;
- and
- (g) forming source contacts on said source regions.
Dependencies are inferred from the claim text.