Self-aligned trenched contact (satc) process

The method of forming a self-aligned trenched contact in the fabrication of an integrated circuit comprising:

• forming semiconductor device regions in and on a semiconductor substrate wherein said semiconductor device regions include gate electrodes on the surface of said semiconductor substrate and source/drain regions within said semiconductor substrate;
• forming spacers on the sidewalls of said gate electrodes;
• depositing a layer of silicon oxide over the surface of said substrate wherein said silicon oxide layer contacts said source/drain regions within said substrate between said gate electrodes;
• covering said substrate with a layer of photoresist and patterning said photoresist to provide an opening between said gate electrodes;
• etching away said silicon oxide using said patterned photoresist and said sidewall spacers as a mask to provide an opening to said semiconductor substrate where said self-aligned trenched contact will be formed;
• etching a trench into said semiconductor substrate within said opening using said sidewall spacers as a mask to form said self-aligned trenched opening wherein the depth of said trench within said semiconductor substrate is greater than about 0.25 microns and preferably greater than 0.5 microns;
• and
• depositing a layer of polysilicon over the surface of said substrate and within said trenched opening wherein said polysilicon layer is ion implanted and wherein outdiffusion forms an N+ contact diffusion region surrounding said trench within said semiconductor substrate to complete said contact in the manufacture of said integrated circuit device.

The method of forming a self-aligned trenched contact in the fabrication of an integrated circuit comprising:

• forming semiconductor device regions in and on a semiconductor substrate wherein said semiconductor device regions include gate electrodes on the surface of said semiconductor substrate and source/drain regions within said semiconductor substrate;
• forming spacers on the sidewalls of said gate electrodes;
• depositing a layer of silicon oxide over the surface of said substrate wherein said silicon oxide layer contacts said source/drain regions within said substrate between said gate electrodes;
• covering said substrate with a layer of photoresist and patterning said photoresist to provide an opening between said gate electrodes;
• etching away said silicon oxide using said patterned photoresist and said sidewall spacers as a mask to provide an opening to said semiconductor substrate where said self-aligned trenched contact will be formed;
• etching a trench into said semiconductor substrate within said opening using said sidewall spacers as a mask to form said self-aligned trenched opening wherein the depth of said trench within said semiconductor substrate is greater than about 0.25 microns and preferably greater than 0.5 microns;
• implanting ions into said trench and heating said substrate to drive said ions into the region within said substrate surrounding said trench;
• and
• depositing a metal layer over the surface of said substrate and within said trench to complete said contact in the manufacture of said integrated circuit device.