Fabrication of w-polycide-to-poly capacitors with high linearity

A method for forming an integrated circuit in and on a silicon substrate, with a polycide-to-polysilicon capacitor and with a CMOS device with polycide gate, comprising:

• forming field oxide regions, n-well and p-well regions, and gate oxide regions in and on said silicon substrate;
• forming a first doped polysilicon layer on said gate oxide and said field oxide regions;
• depositing a layer of silicide on said first doped polysilicon layer;
• annealing said layer of silicide;
• patterning said first doped polysilicon layer and said silicide layer to form gate electrode of said CMOS device, and to form a polycide bottom plate of said polycide-to-polysilicon capacitor;
• forming lightly-doped drain regions in said CMOS device;
• forming sidewalls on said gate electrode and on said polycide bottom plate;
• ion implanting in a vertical direction into said polycide bottom plate;
• ion implanting in a vertical direction into said lightly-doped drain regions of said CMOS device;
• ion implanting remaining active regions of said CMOS device with a second and opposite conductivity-imparting dopant;
• depositing an interpoly oxidation layer on the surfaces of said polycide bottom plate, said CMOS device, and said field oxide regions, to act as a dielectric for said polycide-to-polysilicon capacitor, and to isolate said CMOS device from subsequent layers;
• densifying said interpoly oxidation layer;
• forming a second doped polysilicon layer over the surface of said interpoly oxidation layer;
• patterning said second doped polysilicon layer to form a polysilicon top plate of said polycide-to-polysilicon capacitor, having a suitable doping concentration;
• and
• forming remaining layers to complete said integrated circuit.