Process for forming a static-random-access memory cell
AssigneeMotorola, Inc.
InventorsJames R. Pfiester, James D. Hayden
Life of this patent
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Abstract
An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.
Claims10
A process for forming a static-random-access memory cell comprising the steps of:
- providing a semiconductor substrate having:
- a first conductivity type;
- a primary surface;
- and
- first, second, third, and fourth regions adjacent to the primary surface,
- wherein the first and third regions lie adjacent to each other and
- the second and fourth regions lie adjacent to each other;
- doping the first region with a first dopant to a first dose, wherein the first
- dopant has the first conductivity type;
- doping the second region with a second dopant to a second dose, wherein:
- the second dopant has the first conductivity type;
- and
- the first dose is heavier than the second dose;
- forming a field isolation region over the first and second regions and adjacent
- but not over the third and fourth regions;
- forming a gate dielectric layer over the third and fourth regions;
- forming first and second conductive members over the gate dielectric layer,
- wherein:
- the first conductive member overlies the third region and acts as a gate
- electrode for a pass transistor;
- and
- the second conductive member overlies the fourth region and acts as a
- gate electrode for a latch transistor;
- and forming fifth regions to form the pass and latch transistors, wherein:
- the fifth regions lie adjacent to the primary surface and sides of the first
- and second conductive members;
- the fifth regions have a second conductivity type that is opposite the
- first conductivity type.
A process for forming a memory array including a plurality of static-random-access memory cells comprising the step of:
- providing a semiconductor substrate having:
- a first conductivity type;
- a primary surface;
- and
- first, second, third, and fourth regions adjacent to the primary surface,
- wherein the first and third regions are adjacent to one another and the second and fourth regions are
- adjacent to one another;
- doping the first regions with a first dopant to a first dose, wherein the
- first dopant has the first conductivity type;
- doping the second regions with a second dopant to a second
- dose, wherein:
- the second dopant has the first conductivity type;
- and
- the first dose is heavier than the second dose;
- forming at least one field isolation region, wherein the at least one field
- isolation overlies the first and second regions and adjacent but
- not over the third and fourth regions;
- forming a gate dielectric layer over the third and fourth regions;
- forming first and second conductive members over the gate dielectric layer,
- wherein:
- the first conductive member acts as gate electrodes for pass transistors
- and as a word line for the memory array;
- and
- each of the second conductive members act as a gate electrode for a latch transistor;
- forming fifth regions to form pass and latch transistors, wherein:
- the fifth regions lie adjacent to the primary surface and sides of the first
- and second conductive members;
- and
- the fifth regions have a second conductivity type that is opposite the
- first conductivity type;
- forming an insulating layer over the pass and latch transistors;
- and
- forming load components over the insulating layer, wherein the load
- components are selected from a group consisting of resistors,
- transistors, and diodes.
Dependencies are inferred from the claim text.