Method of manufacturing a stacked capacitor DRAM
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKaoru Motonami, Yoshinori Okumura
Life of this patent
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Abstract
A storage node of a stacked capacitor in a DRAM comprises a first part connected to a source/drain region and a second part protruding upward from a substrate in a vertical wall shape. The second part includes a concave part in the inner part which is removed by etching. Steps are formed on the inner and outer peripheral surfaces of the vertical wall part. The steps are formed by a self-alignment method using a sidewall insulating layer formed by anisotropic etching. Capacitance of the capacitor is increased by forming steps on the surface of the storage node.
Claims6
A method of manufacturing a DRAM having a stacked capacitor connected to impurity regions formed on a main surface of a semiconductor substrate comprising the steps of:
- forming a first insulating layer on a main surface of a semiconductor substrate including impurity regions formed therein to have an opening which reaches said impurity regions;
- forming a first conductive layer on the surface of said first insulating layer and inside said opening;
- forming an opening region on the periphery of an region of said first conductive layer to be a lower electrode of one stacked capacitor to reach said first insulating layer;
- forming a second insulating layer in said opening region;
- etching said first conductive layer so that the upper part of said second insulating layer protrudes from the surface of said first conductive layer;
- forming a sidewall insulating layer on the side surface of said second insulating layer protruding from the surface of said first conductive layer;
- etching said first conductive layer using said sidewall insulating layer as a mask to form a concave part in the inner part of said first conductive layer;
- removing said second insulating layer and said sidewall insulating layer and then forming a dielectric layer on the surface of said first conductive layer;
- and
- forming a second conductive layer on the surface of said dielectric layer.
A method of manufacturing a DRAM having a stacked capacitor connected to an impurity region formed in a main surface of a semiconductor substrate comprising the steps of:
- forming a first insulating layer on a main surface of a semiconductor substrate including impurity regions formed therein to have an opening which directly contacts said impurity region;
- forming a first conductive layer on the surface of said first insulating layer and inside said opening;
- forming an opening region which reaches said first insulating layer on the periphery of a region of said first conductive layer to be a lower electrode of one stacked capacitor;
- after forming the opening region, selectively forming a mask layer for etching on the surface of said first conductive layer surrounded by said opening region;
- etching said first conductive layer using said mask layer for etching as a mask to form a concave part in the surface of said first conductive layer uncovered with said mask;
- forming a dielectric layer on the surface of said first conductive layer;
- and
- forming a second conductive layer on the surface of said dielectric layer.
Dependencies are inferred from the claim text.