Providing various electrical protections to a CMOS integrated circuit
AssigneeIntel Corporation
InventorsJames W. Alexander, Louis Johnson
Life of this patent
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Abstract
The electrical protection circuit disclosed comprises a latchup detection circuit, a threshold detector, an oscillator, a charge pump, a switching circuit, a voltage reference and detection circuit, and a signaling circuit. The latchup detection circuit, the threshold detector, the oscillator, the charge pump, and the switching circuit cooperate to provide latchup protection for the CMOS integrated circuit. The switching circuit provides integrated reverse current protection to the CMOS integrated circuit. The voltage reference and detection circuit, the threshold detector, and the signaling circuit provides low voltage protection for the SRAM-based software-downloaded Field Programmable Gate Array of the CMOS integrated circuit.
Claims12
A circuit for protecting a CMOS integrated circuit from latching up as a result of improper application of power to said CMOS integrated circuit, said CMOS integrated circuit receiving power supplies from more than one power source, said circuit comprising:
- a) a latchup detection circuit coupled to said power sources of said CMOS integrated circuit for detecting certain predetermined power differential pattern between a first and the remainder of said power sources and sourcing a first output current in response;
- b) a threshold detector coupled to said latchup detection circuit and said first power source for receiving said first output current from said latchup detection circuit and power from said first power source, and sourcing a second output current in response;
- c) an oscillator coupled to said threshold detector and said first power source for receiving said second output current from said threshold detector and power from said first power source, and alternatingly sourcing a third and a fourth output current in response;
- d) a charge pump coupled to said oscillator and said first power source for receiving said third and fourth output current alternatingly from said oscillator and power from said first power source, and providing a steady output voltage larger than said first power source' voltage;
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- e) a switching circuit coupled to said charge pump, said first power source, and said CMOS integrated circuit for receiving said steady output voltage from said charge pump and power from said first power source, and closing itself in response, allowing said power from said first power source to be provided to said CMOS integrated circuit.
A circuit comprising:
- a) state indicating means coupled to a first and a second power source comprising a silicon controlled rectifier for indicating one of two states, said state indicating means having the following state transition rules:
- a.1) if said state indicating means is in a first state and said second power source is on, said state indicating means stays in said first state;
- a.2) if said state indicating means is in said first state, said second power source is off, and said first power source is on, said state indicating means goes into a second state;
- a.3) if said state indicating means is in said second state and said first power source is on, said state indicating means stays in said second state;
- a.4) if said state indicating means is in said second state and said first power source is off, said state indicating means goes into said first state;
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- b) enabling means coupled to said state indicating means, said first power source, and a CMOS integrated circuit for sourcing power from said first power source to said CMOS integrated circuit when said state indicating means is in said second state, and depriving power from said first power source to said CMOS integrated circuit when said state indicating means is in said first state.
Dependencies are inferred from the claim text.