Fractionally-spaced equalizer for a DS-CDMA system

A direct-sequence multiple-access code division (DS-CDMA) communication system comprising:

• a multiplicity of transmitters, each of said transmitters including:
• a CDMA waveform signal generator that generates a CDMA waveform signal, said CDMA waveform signal comprising an RF carrier signal modulated with a first bandwidth informational data signal comprising a sequence of data bits, each data bit having a bit time of T.sub.B, and each data bit being modulated with a second bandwidth waveform signature signal, said waveform signature signal comprising a train of N.sub.C chip pulses, each chip pulse being separated from an adjacent chip pulse by T.sub.C seconds such that N.sub.C .multidot.T.sub.C =T.sub.B, each chip pulse of said train of chip pulses having an amplitude set by a binary spreading code unique to each transmitter;
• a transmitter that transmits the CDMA waveform signal from each of said multiplicity of transmitters so that the chip pulses are transmitted having a spectrally inefficient substantially non-flat power spectrum within a band .+-.1/T.sub.C ;
• and
• a receiver comprising:
• an RF receiver that receives the CDMA waveform signals transmitted from each of said multiplicity of transmitters and strips the RF carrier signal therefrom, thereby leaving a data input signal to said receiver that comprises said sequence of data bits, with each data bit being modulated with the waveform signature that is unique to each transmitter;
• a sampling circuit that samples the data input signal at a prescribed sampling rate to produce a series signal x.sub.m ;
• an adaptive filter coupled to receive said series signal x.sub.m and subject it to a prescribed transfer function that produces a filtered output signal y.sub.m, said transfer function being adapted to compensate for the spectrally inefficient substantially non-flat power spectrum of the transmitted chip pulses within the band .+-.1/T.sub.C, and to compensate the series signal x.sub.m for signal distortions caused by multiple signal paths of the CDMA waveform signal as it is transmitted from the transmitter to the receiver;
• a decimator circuit that decimates the filtered output signal y.sub.m by a prescribed decimation factor D to produce a decimated series signal z.sub.n ;
• timing acquisition means responsive to the series signal x.sub.m for generating the binary spreading code of a user of interest and a timing signal that controls when within a data bit of said data input signal the sampling means samples the data input signal;
• a despreading circuit connected to said decimator circuit and responsive to said timing signal that identifies the beginning and ending points of a data bit within said series signal z.sub.n that originates with said user of interest and that multiplies the series signal z.sub.n by an aligned spreading code c.sub.n ;
• and
• an accumulator that accumulates the series signal z.sub.n, as multiplied by the spreading code c.sub.n, over the data bit to produce a data decision signal.

A fractionally-spaced equalizer for use within a receiver of a code-division multiple-access (CDMA) communication system, said CDMA communication system including a multiplicity of transmitters adapted to transmit data bit signals to said receiver, each transmitter of said multiplicity of transmitters having means for modulating its transmitted data bits with a prescribed signature waveform, each transmitter further having its data bit signals transmitted having a spectrally inefficient, substantially non-flat, power spectrum within a band .+-.1/T.sub.C, where T.sub.C is a chip time associated with the prescribed signature waveform, said equalizer comprising:

• a series of 2L delay elements, where L is a positive integer, each for delaying an input signal applied to an input port thereof by an amount T.sub.H, a first delay element having an input port to which the input signal is applied, and an output port connected to the input port of an adjacent delay element, whereby the input signal is delayed by a total delay of 2LT.sub.H as it is passed through said series of delay elements from the first delay element to a second delay element, from the second delay element to a third delay element, and so on, to the last delay element, each of said delay elements having a tap point on both sides thereof, whereby 2L+1 tap points are provided;
• means for coupling a transmitted data bit signal received by said receiver to the input port of the first delay element;
• a series of 2L+1 multiplier elements, each multiplier element of said series of 2L+1 multiplier elements having first and second input ports and an output port, with the signal at the output port being the product of the signals applied to the first and second input ports, the first input port of each multiplier element of said first series being connected to a respective tap point;
• an accumulation circuit having 2L+1 input terminals and an output terminal, said accumulation circuit providing a sum signal at its output terminal that is the sum of the signals applied to each of its 2L+1 input terminals, said 2L+1 input terminals being connected to the output port of a corresponding one of said first series of 2L+1 multiplier elements;
• a series of 2L+1 tap processing networks, each network of said series of 2L+1 tap processing networks having first, second, and third input terminals, and an output terminal, the output terminal providing a signal that represents a prescribed function of signals applied to the first, second, and third input terminals, said first input terminal being connected to the tap point of a respective one of said 2L+1 delay elements, the second input terminal being connected to an error signal, the third input terminal being connected to a fixed control signal, and the output terminal being connected to the second input port of a respective one of said first series of 2L+1 multiplier elements;
• a difference circuit having a negative input terminal, a positive input terminal, and an output terminal, a difference signal being provided at its output terminal that represents the difference between a signal applied to the negative input terminal and a signal applied to the positive input terminal, the negative input signal of said difference circuit being connected to the output terminal of the summation circuit, the positive input terminal being connected to a signal representative of a prescribed chip waveform associated with a known user of said CDMA system, and the output terminal being applied to the second input terminal of each of said 2L+1 tap processing networks, the difference signal generated by said difference circuit thereby comprising said error signal;
• the signal appearing at the output terminal of said accumulation circuit representing an output signal of said fractionally-spaced equalizer;
• the combination of signals appearing at the respective output terminals of the 2L+1 tap processing networks comprising a set of tap weight signals that adaptively tune said fractionally-spaced equalizer to compensate for the spectrally inefficient, substantially non-flat, power spectrum of the transmitted data bit signals;
• and
• means for setting the fixed control signal applied to the second input terminal of the 2L tap processing networks to a value that maximizes the signal-to-noise ratio of the output signal.

An adaptive filter for use within a receiver of a code-division multiple-access (CDMA) communication system, said CDMA communication system including a multiplicity of transmitters, each adapted to transmit a data bit signal to said receiver, and each transmitter having means for modulating the individual bits of its transmitted data bit signal with a prescribed chip waveform, and each transmitter further having its data bit signal transmitted having a spectrally inefficient, substantially non-flat, power spectrum within a band .+-.1/T.sub.C, where T.sub.C is a chip time associated with the prescribed chip waveform, said adaptive filter comprising:

• first and second digital filters, each having a signal input port, a signal output port, an error signal port, and a set of signal tap ports, each further having means for processing an input signal applied to its input port in accordance with a prescribed discrete transfer function to produce an updated output signal as a function of prior signals present at its signal output port, error signal port, and signal tap ports, with the set of signal tap ports of each digital filter being adapted to compensate for the spectrally inefficient, substantially non-flat, power spectrum of the transmitted data bit signal;
• first and second comparison circuits, each having a first input terminal, a second input terminal, and an output terminal, and each providing an error signal that appears at its output terminal as a function of the relationship between signals applied to its first and second input terminals, the first input terminal of each comparison circuit being connected to the output port of a corresponding one of said first and second digital filters, and the output terminal of each comparison circuit being connected to the error signal port of a corresponding one of said first and second digital filters, the second input terminals of each comparison circuit being coupled to a positive reference chip signal and a negative reference chip signal, respectively;
• a multiplexer circuit having first and second sets of input terminals, a set of output terminals, and a control terminal, with the set of output terminals being switchably connected to a selected one of the first or second sets of input terminals as a function of a control signal applied to said control terminal, said first and second sets of input terminals being connected respectively to the first and second sets of signal tap ports of the first and second digital filters, and said set of output terminals also being connected to the first and second sets of signal tap ports of both said first and second digital filters, whereby a selected one of the set of tap signals present in said first and second digital filters at the conclusion of a processing time interval is used by both of said first and second digital filters at the beginning of a next processing time interval;
• means for coupling the transmitted data bit signal received at said receiver to the input signal port of both of said first and second fractionally-spaced equalizers;
• and
• means for generating said control signal as a function of a most recent bit decision of said transmitted data bit signal.

A method of detecting with a maximized signal-to-noise ratio (SNR) whether the bits of a transmitted data sgnal used within a code-division multiple access (CDMA) communications system represent a digital "1" or a digital "0", said CDMA communications system including a plurality of transmitters, each of which includes means for transmitting data signals at the same data rate and bandwidth as may be transmitted by others of the transmitters at the same time, and a base-station receiver adapted to receive said transmitted data signals, said method comprising the steps of:

• (a) generating a sequence of chip pulses that define a unique chip sequence within each bit time of the data signal to be transmitted, said unique chip sequence serving to identify a particular transmitter from which the transmitted signal originates;
• (b) shaping the chip pulses of each sequence of chip pulses generated in step (a) so that each has a spectrally inefficient, substantially non-flat, power spectrum within a band .+-.1/T.sub.C, where T.sub.C is a chip time between the chip pulses of the sequence of chip pulses;
• (c) transmitting the sequence of chip pulses shaped in step (b) as part of each data bit that is transmitted by the particular transmitter, whereby each data bit transmitted is encoded with said unique chip sequence;
• (d) receiving the sequence of chip pulses at the receiver;
• (e) passing the sequence of chip pulses received in step (d) through a matched filter, said matched filter having a frequency response adapted to match the powr spectrum of the transmitted chip pulses;
• (f) sampling the sequence of chip pulses passed through the matched filter in step (e) at a Nyquist rate to produce a sampled series of pulses, x.sub.m (i);
• (g) passing the sampled series of pulses, x.sub.m (i), through a first fractionally spaced equalizer adapted to produce a sequence of pulses y.sub.m (i), said first fractionally-spaced equalizer being configured to exhibit a frequency response that compensates for the spectrally inefficient, substantially non-flat shape of the power spectrum of the transmitted pulses, and to adaptively compensate for signal distortions that occur in said sequence of chip pulses while en-route to said receiver, so as to produce a net frequency response for the series of pulses y.sub.m (i) that is substantially flat over all frequencies of interest, thereby maximizing the SNR of the series y.sub.m (i), and that automatically compensates for signal distortions;
• and
• (h) determining whether the sequence of pulses y.sub.m (i) represents a data bit that is a digital "1" or a digital "0".