US 5,367,187 A · Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions

Abstract

The input/output circuit cells of a master-slice gate array device have the same diffusion and gate regions as the basic transistors so that the input/output of the device may be defined at the metallization stage rather than at the time the diffusion regions are formed. Thus a single size master-slice circuit device need to be kept in inventory. The array size is selected in accordance with the customer's specification and the inputs/outputs are defined accordingly using CAD. Thereafter, the die may be scribed into smaller. The transistors for sea-of-gate structures containing a pair of long channel transistors whose drain, gate and source regions lie on a single grid or track of the CAD design tool. By using a long channel transistor in the feedback loop of a memory cell, gating transistors may be eliminated to reduce transistors required for latches. To provide the required drive capability, a number of transistors may be connected to form the input or output buffer, without requiring large transistors with large diffusion regions. A metal silicide resistor and a number of discharge transistors normally in the off condition are connected to the node between an input/output pad and input/output buffer for electrostatic discharge.

Claims23

Dependent claims

A master-slice gate array integrated circuit device comprising;

a semiconductor medium;
and
an array of basic transistors in the medium forming sea-of-gate structures, wherein said sea-of-gate structures each comprises a plurality of wide channel transistors whose channel length is less than channel width and at least one pair of long channel transistors whose channel length is at least four times greater than its channel width.

A master-slice gate array circuit comprising:

a semiconductor substrate;
a multiplicity of basic cells formed on the substrate, each basic cell including at least one long channel transistor and a plurality of wide channel transistors;
wherein the channel length of each at least one long channel transistor is greater than its channel width;
and
wherein the channel width of each wide channel transistor is greater than its channel length;
wherein each respective basic cell includes a respective column of n-type wide channel transistors in which adjacent n-type wide transistors channel share common source/drain regions, a respective column of p-type wide channel transistors in which adjacent p-type wide channel transistors share common source/drain regions, at least one n-type long channel transistor and at least one p-type long channel transistor;
wherein horizontal and vertical grid lines form a coordinate system used for placing and routing interconnect lines;
and
wherein for each respective basic cell, source/drains of respective n-type wide channel transistors and source/drains of respective p-type wide channel transistors share respective first horizontal grid lines and respective n-type long channel transistors and respective p-type long channel transistors share respective second horizontal grid lines.

6 more elements

Dependencies are inferred from the claim text.

Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions

Life of this patent

Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions

Life of this patent

Abstract

Claims23