Potentiometric oscillator with reset and test input

A phase-lock loop circuit for generating a clock signal in response to a reference signal, said phase-lock loop circuit comprising:

• phase frequency detector for determining a phase difference between said clock signal and said reference signal, said phase frequency detector generating a phase difference signal indicative of said phase difference;
• a filter electrically coupled to said phase frequency detector for receiving said phase difference signal and for generating a control signal in response to said phase difference signal;
• a feedback divider electrically coupled to said phase frequency detector for feeding back a divided clock signal from said clock signal to said phase frequency detector;
• voltage-controlled oscillator electrically coupled with said filter for receiving said control signal and for generating said clock signal at a frequency responsive to said control signal, said voltage-controlled oscillator being electrically coupled with said feedback divider for transmitting said clock signal to said feedback divider, said voltage-controlled oscillator comprising:
• a plurality of multiplexers coupled in series, said plurality of multiplexers including a first multiplexer and a last multiplexer, each of said plurality of multiplexers having a signal input, a select input, and a signal output, said signal input of each of said plurality of multiplexers except said first multiplexer being electrically coupled with said signal output of a previous multiplexer of said plurality of multiplexers for receiving one of a first and second input signal from said previous multiplexer, said second input signal being said first input signal with a predetermined delay, said signal output of each of said plurality of multiplexers except said last multiplexer being electrically coupled with said signal input of a next multiplexer of said plurality of multiplexers for propagating one of said first and second input signals to said next multiplexer in response to a select signal applied at said select input, said last multiplexer generating said one of said first and second input signals as an output signal in response to said select signal applied at its select input;
• a test circuit for generating a test signal of predetermined logic level;
• a 3-input multiplexer having first, second and third signal inputs, a select input, and a signal output, said first and second signal input of said 3-input multiplexer being electrically coupled with said signal output of said last multiplexer for receiving said output signal, said signal output of said 3-input multiplexer being electrically coupled with said signal input of said first multiplexer, wherein said plurality of multiplexers and said 3-input multiplexer form a ring oscillator, said 3-input multiplexer receiving said first and second input signals at said first and second signal inputs of said 3-input multiplexer from said last multiplexer of said plurality of multiplexers and receiving said test signal as a third input signal at said third signal input, said 3-input multiplexer propagating one of said first, second and third input to said first multiplexer of said plurality of multiplexers;
• a selecting circuit electrically coupled with said select input of each of said plurality of multiplexers and said select input of said 3-input multiplexer for generating said select signal to select one of said first and second input signals, said selected input signal being propagated through said ring oscillator;
• and
• an initiator electrically coupled with said 3-input multiplexer for generating an initiate signal to select said test signal to be generated at said signal output of said 3-input multiplexer, said initiate signal overriding said select signal such that said test signal propagates through said ring oscillator with said predetermined logic level.

A phase-lock loop circuit with a test mode for generating a clock signal in response to a reference signal, said test mode causing the components of said phase-lock loop circuit to be tested, said phase-lock loop circuit comprising:

• phase frequency detector for receiving said reference signal and for determining a phase difference between said clock signal and said reference signal, said phase frequency detector generating a phase difference signal indicative of said phase difference;
• a filter electrically coupled to said phase frequency detector for receiving said phase difference signal and for generating a control signal in response to said phase difference signal;
• a feedback divider electrically coupled to said phase frequency detector for feeding back a divided clock signal from said clock signal to said phase frequency detector;
• voltage-controlled oscillator electrically coupled with said filter for receiving said control signal and for generating said clock signal at a frequency responsive to said control signal, said voltage-controlled oscillator being electrically coupled with said feedback divider for transmitting said clock signal to said feedback divider, said voltage-controlled oscillator comprising:
• a plurality of multiplexers coupled in series, said plurality of multiplexers including a first multiplexer and a last multiplexer, each of said plurality of multiplexers having a signal input, a select input, and a signal output, said signal input of each of said plurality of multiplexers except said first multiplexer being electrically coupled with said signal output of a previous multiplexer of said plurality of multiplexers for receiving one of a first and second input signal from said previous multiplexer, said second input signal being said first input signal with a predetermined delay, said signal output of each of said plurality of multiplexers except said last multiplexer being electrically coupled with said signal input of a next multiplexer of said plurality of multiplexers for propagating one of said first and second input signals to said next multiplexer in response to a select signal applied at said select input, said last multiplexer generating said one of said first and second input signals as an output signal in response to said select signal applied at its select input;
• a 3-input multiplexer having first, second and third signal inputs, a select input, and signal output, said first and second signal input of said 3-input multiplexer being electrically coupled with said signal output of said last multiplexer for receiving said output signal, said signal output of said 3-input multiplexer being electrically connected with said signal input of said first multiplexer, wherein said plurality of multiplexers and said 3-input multiplexer form a ring oscillator, said 3-input multiplexer receiving said first and second input signals at said first and second signal inputs of said 3-input multiplexer from said last multiplexer of said plurality of multiplexers and receiving said reference signal as a third input signal at said third signal input, said 3-input multiplexer propagating one of said first, second and third input signals to said first multiplexer of said plurality of multiplexers;
• a selecting circuit electrically coupled with said select input of each of said plurality of multiplexers and said select input of said 3-input multiplexer for generating said select signal to select one of said first and second input signals, said selected input signal being propagated through said ring oscillator;
• and
• a test mode selecting circuit coupled to said 3-input multiplexer for receiving a test mode signal to select said reference signal for generation at said signal output of said 3-input multiplexer, said test mode signal overriding said select signal such that said reference signal propagates through said ring oscillator.