US 5,353,429 AGranted

Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller

AssigneeApple Computer, Inc.

InventorJonathan M. Fitch

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Abstract

A memory system where a cache miss is fielded with a retry access to main memory, but instead of waiting for the microprocessor to resynchronize and re-initiate the memory cycle, the memory cycle is started immediately. The speed of the tag array is specified so that the status of the cache, hit or miss, is known at the same time that the microprocessor's memory cycle start signal is known to be valid. The addresses are then latched and the memory cycle is started in anticipation of the retried cycle. The access time of memory is then overlapped with microprocessor resynchronization and memory cycle reinitialization. By using this technique, clock cycles are needed for the initial cycle, additional clock cycles are needed to perform the resynchronization, and additional clock cycles are needed for the retried cycle since the data is already waiting from memory. The above-described improvement is implemented by decoupling the direct connection of the memory array from the address bus. Additionally, a state machine modifies the operation of the memory controller so that the access time of the memory is overlapped with microprocessor resynchronization and memory cycle reinitialization.

Claims5

Dependent claims

A computer system including a cache memory system comprising:

a) a central processing unit coupled to a data bus and an address bus;
b) a main memory having a predetermined access time coupled to said data bus and to an address latch bus, said main memory for storing data and instructions for use by said central processing unit;
c) a memory controller means for controlling accesses to said main memory, said memory controller means including i) an address latch coupled to said address bus and said address latch bus, and ii) state machine means for controlling the operation of the memory controller means and the address latch;
d) a cache memory means coupled to said address bus and said data bus for storing a predetermined subset of said data and instructions for use by said central processing unit;
e) a cache tag array means coupled to said address bus for storing portions of addresses from said address bus corresponding to addresses of data and instructions stored in said cache memory means and for generating signals indicating for an address on said address bus whether data corresponding to the address on the address bus is stored within said cache memory means, such that if said data corresponding to the address on the address bus is not stored within said cache memory means, said state machine operates to cause the access time of said main memory to be overlapped with resynchronization of said central processing unit and memory cycle reinitialization required to obtain the data from said main memory.

2 more elements

Dependencies are inferred from the claim text.