Information processing apparatus in which a cache memory can be operated in both store-in and store-through modes
AssigneeHitachi, Ltd.
InventorMasabumi Shibata
Life of this patent
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AssigneeHitachi, Ltd.
InventorMasabumi Shibata
Estimating the term…
In an information processing apparatus composed of two or more processor units each including a cache memory and a processor which accesses stored data via the cache memory, and a main storage, a cache memory control method in which, using information concerning control object data, such as identification of a storage area and whether or not the data are program data, a judgment is made as to whether or not the data has a high possibility of being used by another processor. If the data has a high possibility of being used by another processor, the cache memory is controlled by the store-through system. If the data has a low possibility of being used by another processor, the cache memory is controlled by the store-in system.
An information processing apparatus comprising:
A cache memory control method for use in an information processing apparatus composed of a main storage, for storing a plurality of blocks of data, and a plurality of processor units, said processor units each including a processor having a control status register for storing information about the processor's control status, a private cache memory associated with said processor and said main storage, and a cache memory controller associated with said processor and said private cache memory, said method comprising the steps of:
An information processing apparatus comprising:
An information processing apparatus for performing a plurality of processes, said information processing apparatus comprising:
Dependencies are inferred from the claim text.