US 5,353,427 AGranted

Semiconductor memory device for simple cache system with selective coupling of bit line pairs

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsKazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura

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Abstract

A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

Claims22

Dependent claims

A semiconductor memory device containing a cache memory, comprising, on a single chip:

a first memory cell array comprising a plurality of word lines, a plurality of bit line pairs perpendicular to said plurality of word lines and a plurality of memory cells arranged in a matrix of a plurality of rows corresponding to said word lines and columns corresponding to said bit line pairs, said first memory cell array being divided into a plurality of blocks each comprising a plurality of columns,
a cache memory including a second memory cell array comprising a plurality of static type memory cells arranged in a plurality of rows and a plurality of columns, said second memory cell array being divided into a plurality of blocks each comprising a plurality of columns, each said static type memory cell being structurally aligned with a column of said first memory cell array and connectable to each one of a subset of said plurality of bit line pairs of said first memory cell array in response to a predetermined selecting signal,
first access means responsive to a cache miss indicating signal for accessing data at a memory cell of said first memory cell array selected by a first row address signal and a column address signal, said first access means comprising block selecting means responsive to a block selecting signal for selecting any of said plurality of blocks in said first memory cell array,
second access means responsive to a cache hit indicating signal for accessing data at a static type memory cell selected by a second row address signal and a column address signal, and
data transfer means for transferring data between a column in said first memory cell array and a respective column in said second memory cell array.

2 more elements

A semiconductor memory device containing a cache memory, comprising, on a single chip:

a first memory cell array comprising a plurality of word lines, a plurality of bit line pairs perpendicular to said plurality of word lines and a plurality of memory cells arranged in a matrix of a plurality of rows corresponding to said word lines and columns corresponding to said bit line pairs, said first memory cell array being divided into a plurality of blocks each comprising a plurality of columns,
a cache memory including a second memory cell array comprising a plurality of blocks, each block having a plurality of static type memory cells arranged in one or more rows and a plurality of columns each corresponding to, and connectable to, one column included in each of said blocks of said first memory cell array in response to a predetermined selecting signal, each of said columns of said static type memory cells being structurally aligned with one of said bit line pairs,
first access means responsive to a cache miss indicating signal for accessing data at a memory cell of said first memory cell array selected by a first row address signal and a column address signal, said first access means comprising block selecting means responsive to a block selecting signal for selecting any of said plurality of blocks in said first memory cell array,
second access means responsive to a cache hit indicating signal for accessing data at a static type memory cell selected by a second row address signal and a column address signal, and
data transfer means for transferring data from memory cells in a row of a block of said first memory cell array selected by said block selecting means to memory cells in a row of a selected block of said second memory cell array.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/063,487Filed 19 May 1993 · division
Priority: JP 62-2816196 Nov 1987
Granted: 4 Oct 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/0893
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: caches…
G11C 7/1021
Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters: page serial bit line…
G06F
Computing and data processing
G11C
Static stores

Family

Serial266,601Parent of this continuation · filed 3 Nov 1988
Serial564,657Parent of this division · filed 9 Aug 1990
US 5,226,147 AParent of this division
US 5,353,427 AThis patent

From the US filing history. Foreign family members aren’t listed.

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