US 5,353,426 A · Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to complete

Abstract

A cache array, a cache tag and comparator unit and a cache multiplexor are provided to a cache memory. Each cache operation performed against the cache array, read or write, takes only half a clock cycle. The cache tag and comparator unit comprises a cache tag array, a cache miss buffer and control logic. Each cache operation performed against the cache tag array, read or write, also takes only half a clock cycle. The cache miss buffer comprises cache miss descriptive information identifying the current state of a cache fill in progress. The control logic comprises a plurality of combinatorial logics for performing tag match operations. In addition to standard tag match operations, the control logic also conditionally tag matches an accessing address against an address tag stored in the cache miss buffer. Depending on the results of the tag match operations, and further depending on the state of the current cache fill if the accessing address is part of the memory block frame of the current cache fill, the control logic provides appropriate signals to the cache array, the cache multiplexor, the main memory and the instruction/data destination. As a result, subsequent instruction/data requests that are part of a current cache fill in progress can be satisfied without having to wait for the completion of the current cache fill, thereby further reducing cache miss penalties and function unit idle time.

Claims18

Dependent claims

In a computer system, a method for caching instruction/data that further reduces cache miss penalties, said method comprising the steps of:

a) storing a plurality of memory block frames of a main memory of said computer system in a plurality of cache lines of a cache array;
b) storing a plurality of address tags for said cached memory block frames in a plurality of cache tag entries of a cache tag array corresponding to said cache lines;
c) storing cache fill descriptive information for a memory block frame of a cache fill in progress in a cache miss buffer;
d) determining cache hit/miss for an instruction/data request using said address tags for said cached memory block frames and said cache fill descriptive information;
and
e) providing appropriate signals to said cache array, said main memory, and a destination for an instruction/data requested by said instruction/data request accordingly such that said instruction/data request is satisfied if said instruction/data requested is part of said memory block frame of said cache fill in progress, without having to wait for said cache fill to be completed, thereby further reducing cache miss penalties.

3 more elements

In a computer system, an apparatus for caching instruction/data that further reduces cache miss penalties, comprising:

a) a cache array coupled to a main memory of said computer system comprising a plurality of cache lines for storing a plurality of memory block frames of said main memory;
b) a cache tag array comprising a plurality of cache tag entries corresponding to said cache lines for storing a plurality of address tags for said cached memory block frames;
c) a cache miss buffer for storing cache fill descriptive information for a memory block frame of a cache fill in progress;
d) control logic coupled to said main memory, said cache array, said cache tag array, and said cache miss buffer for determining cache hit/miss for an instruction/data request using said address tags for said cached memory block frames and said cache fill descriptive information, and providing appropriate signals to said cache array, said main memory, and a destination for an instruction/data requested by said instruction/data request accordingly such that said instruction/data request is satisfied if said instruction/data requested is part of said memory block frame of said cache fill in progress, without having to wait for said cache fill to be completed, thereby further reducing cache miss penalties.

1 more element

Dependencies are inferred from the claim text.

Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to complete

Life of this patent

Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to complete

Life of this patent

Abstract

Claims18