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AssigneeIntel Corporation
InventorSyed A. A. Zaidi
Estimating the term…
In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, and apparatus for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement including apparatus for detecting the appearance of a particular prefixed instruction, apparatus responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, apparatus in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and apparatus for generating a request to the microcontroller to handle microcode vectors generated.
In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed;
The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor having a state machine for detecting and decoding prefixes apart from the decoding of instructions of which they are a part in a decoder circuit, the decoder circuit normally generating a count of the bytes of the instruction not including any prefix bytes for generating a prefetch pointer, comprising the steps of detecting the presence of a prefixed jump instruction, disabling the state machine in response to the detection of the prefixed jump instruction, decoding the prefixed jump instruction in the decoder circuit, generating a microcode vector for the decoded prefixed jump instruction, and increasing the count of the number of bytes in the decoded instruction by one byte.
Dependencies are inferred from the claim text.