Memory-side driven anticipatory instruction transfer interface with processor-side instruction selection

In a computer system including a central processing unit (CPU) and a program memory wherein the CPU experiences a latency delay between requesting an instruction from the program memory and receiving the requested instruction, apparatus which reduces the latency delay comprising:

• instruction preprocessor means, located in proximity to the program memory, for fetching instructions for a program running on the CPU from the program memory and for providing the instructions to the CPU without any CPU driven pre-fetching, said preprocessor means comprising:
• instruction decoder means for assigning a type value to each of the instructions fetched from the program memory;
• instruction path diverger means, responsive to the type value provided by the instruction decoder means, for detecting all instructions which indicate a possible change in an execution sequence of the program and for causing the preprocessor to concurrently provide instructions from execution sequences determined from the detected instructions, the instruction path diverger means comprising:
• branch handling means, for detecting a conditional branch instruction and for identifying a pair of next instructions, of which pair the CPU requests one next instruction following the conditional branch instruction, and
• call handling means, for detecting a call instruction, and for identifying a further instruction which the CPU executes after the CPU executes a return instruction that follows the call instruction;
• storage means coupled to the branch handling means and call handling means for storing a plurality of indicators, the indicators identifying any of the conditional branch instruction, the pair of next instructions, the call instruction and the further instruction, that are detected by either one of the branch handling means and the call handling means;
• and
• memory access control means coupled to the storage means and the program memory for fetching from the program memory a plurality of instruction streams, and for transmitting the plurality of instruction streams without waiting to receive a request from the CPU, the plurality of instruction streams including any of the conditional branch instruction, the pair of next instructions, the call instruction and the further instruction that are identified by the indicators in the storage means;
• and
• means, responsive to instruction requests from the CPU, for selecting and providing the requested instructions to the CPU from among the instruction streams transmitted by the preprocessor means.