CPU lock logic for corrected operation with a posted write array
AssigneeZenith Data Systems Corporation
InventorAnthony M. Olson
Life of this patent
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Abstract
A shared bus arbitration system is disclosed which provides logic allowing multiple processors to co-exist on a common bus. In the present invention, the host processor is isolated from the bus by a posted write array or write buffer. The arbitration system accepts bus lock and cycle signals when the processor writes a locked instruction to the posted write array and provides a bus lock signal to the bus when the locked instructions are written to the bus.
Claims7
A shared bus arbitration system comprising:
- a processor having a self-contained bus lock arbitration capability providing a processor bus lock output, a cycle start output, and a cycle end output, said self-contained bus lock arbitration capability being operative to provide a first processor bus lock signal on said processor bus lock output, a first cycle start signal on said cycle start output, and a first cycle end signal on said cycle end output during a first locked processor cycle and a second processor bus lock signal on said processor bus lock output, a second cycle start signal on said cycle start output and a second cycle end signal on said cycle end output during a second locked processor cycle;
- a write buffer, coupled to a shared bus and to said processor, for asychronously buffering data writes from said processor to said shared bus;
- and
- logic means coupled to said processor bus lock output, said cycle start output, and said cycle end output and responsive to said first processor bus lock signal, said second processor bus lock signal, said first cycle start signal, said second cycle start signal, said first cycle end signal, and said second cycle end signal for selectively providing a shared bus lock signal to said shared bus when data from two consecutive locked processor cycles is written to said shared bus from said write buffer that was written to said write buffer from said processor during consecutive locked processor cycles;
- and
- control means coupled to said shared bus lock signal for granting exclusive access to said shared bus by said write buffer in response to said shared bus lock signal.
A shared bus arbitration system, for controlling access to a shared bus to which is coupled (i) a first processor having internal bus lock logic and providing a first processor bus lock output, a first processor cycle start output, a first processor cycle end output, a first processor bus grant input for granting control of the shared bus and having a first processor bus request output for requesting control of the shared bus, said first processor being operative to provide a first processor bus lock signal on said first processor bus lock output, a first cycle start signal on said first processor cycle start output, and a first cycle end signal on said first processor cycle end output during a first processor cycle and a second processor bus lock signal on said first processor bus lock output, a second cycle start signal on said first processor cycle start output and a second cycle end signal on said first processor cycle end output during a second processor cycle and (ii) a second processor providing a second processor bus request output for requesting control of the shared bus coupled to said first processor bus request output, and having a second processor bus grant input for granting control of the shared bus coupled to said first processor bus grant input;
- said system comprising:
- a write buffer, coupled to said shared bus and to said first processor, for asychronously buffering data writes from said first processor to said shared bus;
- logic means coupled to said processor bus lock output, said cycle start output, and said cycle end output and responsive to said first processor bus lock signal, said second processor bus lock signal, said first cycle start signal, said second cycle start signal, said first cycle end signal, and said second cycle end signal for selectively providing a shared bus lock output when data is written to said shared bus from said write buffer that was written to said write buffer from said processor when said processor bus lock output was active, said logic means further comprising
- means for selectively providing a second cycle lock output responsive to said first processor bus lock output and first processor cycle start output;
- means for selectively providing a first cycle lock output responsive to a first processor bus lock output, and said second cycle end output;
- means for selectively providing said shared bus lock output responsive to said second cycle lock output and said first cycle lock output;
- and
- control means for granting access to said shared bus for a selected one of said processors by asserting a shared bus grant input to said selected one of said processors responsive to said shared bus lock output.
Dependencies are inferred from the claim text.