Method and apparatus for concurrency of bus operations

A computer system which performs concurrent bus cycle operations, comprising:

• a host bus;
• a processor coupled to said host bus;
• a plurality of processor ports storing data;
• a local I/O bus coupled between said processor and said processor ports;
• a cache system coupled between said local I/O bus and said processor and further coupled between said processor and said host bus, said cache system including a cache controller and cache memory, wherein said cache controller snoops said host bus when said cache controller does not control said host bus and generates write-back cycles when a snoop hit occurs to a dirty line in said cache memory;
• cycle generation means coupled to said cache system and said local I/O bus for generating a local I/O cycle after said processor writes or reads data to or from one of said processor ports that does not reside in said cache memory;
• and
• a bus master coupled to said host bus which generates cycles onto said host bus which must be snooped by said cache controller;
• and
• wherein said cache controller snoops said bus master host bus cycle approximately concurrently with said cycle generating means generating said local I/O cycle.

A method for performing concurrent operations in a computer system comprising a host bus;

• a processor coupled to the host bus;
• a bus master coupled to the host bus;
• a cache system coupled between the host bus and the processor, the cache system including a cache controller that snoops host bus cycles when said cache controller does not control said host bus and performs write-back cycles when a snoop hit occurs to a dirty line in said cache memory an expansion bus coupled to the host bus;
• an expansion bus controller coupled between said host bus and said expansion bus;
• and cache interface logic which generates cache controller cycles onto said host bus, the method comprising:
• a) the cache controller generating an expansion bus read cycle including an address of requested data;
• b) the cache interface logic latching said address;
• c) the cache interface logic presenting said address onto the host bus after step b);
• d) the expansion bus controller latching said expansion bus read cycle address after step c);
• e) the bus master performing a host bus cycle that is required to be snooped by the cache controller
• f) the expansion bus controller performing expansion bus cycles to obtain the requested data after step d);
• and
• g) the cache controller snooping said bus master host bus cycle concurrently with step f).