Graphic display processing apparatus and method for improving the speed and efficiency of a window system

A graphic display processing apparatus having a central processing unit (CPU), a video random access memory (VRAM) having a plane structure of one or more planes and adapted to store data, a memory controller adapted to generate an access timing for said VRAM, a drawing controller for transferring the data to said VRAM, and a display system comprised of display means, display address generator means for generating a display address for said VRAM, and display controller for generating a display timing for display of the data on said display means, said graphic display processing apparatus comprising:

• sequential transfer sequence means, coupled to said CPU, for generating an access request timing at set times;
• access cycle generator means for expanding the access request timing from said sequential transfer sequence means into one or more accesses and transferring the accesses to said memory controller;
• a data control unit for designating a processing operation of the data on the basis of an instruction from said CPU under the control of said sequential transfer sequence means and access cycle generator means;
• a data operation unit for performing a processing operation of the data to be drawn on said VRAM on the basis of a command from said data control unit under the control of said access cycle generator means;
• and
• drawing address generator means for generating a drawing address of the data on the basis of a signal from said access cycle generator means;
• wherein said data operation unit is common to a plurality of VRAM's and includes a data structure transformer for transforming the format of the data by using mirror image inversion and swap separately or in combination, a bit mask register for controlling writing to said VRAM in unit of bit, AND means for ANDing the contents of bit mask register and the data of data structure transformer bit by bit, a bit mask shifter for shifting data of said bit mask register, data structure transformer or AND means, a third merge register for holding the previous contents of data of said data structure transformer, a third shifter for shifting data of said data structure transformer and data of said third merge register, and read data synthesizer means for ORing bits of the contents of read data selector means of each plane so as to synthesize read data supplied to said CPU.

A graphic display processing apparatus for a graphic display system having central processing unit (CPU), a video random access memory (VRAM) of a plane structure having a plurality of planes and a memory controller for said VRAM, comprising:

• (1) common to all the planes of said VRAM, a data structure transformer for transforming the format of external data by using mirror image inversion and swap separately or in combination, a bit mask register for controlling writing to said VRAM in unit of bit, AND means for ANDing the contents of bit mask register and the data of data structure transformer bit by bit, a bit mask shifter for shifting data of said bit mask register, data structure transformer or AND means, a third merge register for holding the previous contents of data of said data structure transformer, a third shifter for shifting data of said data structure transformer and data of said third merge register, and read data synthesizer means for ORing bits of the contents of read data selector means of each plane so as to synthesize read data supplied to said CPU;
• and
• a data operation unit including, by the number of planes and so for each plane of said VRAM, read plane selector means for selecting permissibility or impermissibility of reading said VRAM in unit of plane, write plane selector means for selecting permissibility or impermissibility of writing said VRAM in unit of plane, plane bit mask means for synthesizing the output of said write plane selector means and the output of said bit mask shifter and controlling, in unit of bit, writing of each plane of said VRAM, a first buffer register for holding data of said VRAM or data of said data structure transformer as data of a source area, a second buffer register for holding data of said VRAM or data of said data structure transformer as data of a pattern area, a third buffer register for holding data of said VRAM or data of said data structure transformer as data of a destination area, a first merge register for holding the previous contents of data of said VRAM, first buffer register or data structure transformer, a second merge register for holding the previous contents of data of said buffer register of data structure transformer, a first shifter for shifting data of said first buffer register and data of said first merge register, a second shifter for shifting data of said second buffer register and data of said second merge register, a three-value raster operator for performing logical operation by using as inputs the contents of said first and second shifters and the contents of said third buffer register or VRAM, a first two-value raster operator for performing logical operation by using as inputs the contents of said first shifter and the contents of said third buffer register, a second two value raster operator for performing logical operation by using as inputs the contents of said second shifter and the contents of said third buffer register, bit selector means for selecting, when the value of each bit of the output of said third shifter is zero, the output data of said first two-value raster operator at that bit position and selecting, when the value of each bit of the output of said third shifter is one, the output data of said second two-value raster operator at that bit position, write data selector means for supplying the contents of said three-value raster operator or the contents of said bit selector means to said VRAM, and read data selector means for supplying the data of said VRAM or the contents of said three-value raster operator to said read data synthesizing means when the plane is selected by said read plane selector;
• (2) drawing address generator means including a source address register for holding an address of a source area on said VRAM, a destination address register for holding an address of a destination area, a pattern address register for holding an address of a pattern area, a source offset register for holding a value added to the contents of said source address register to update the same when a read access cycle by an access cycle generator ends, a destination offset register for holding a value added to the contents of said destination address register to update the same when a write access cycle by said access cycle generator ends, a pattern offset register for holding a value added to the contents of said pattern address register to update the same when the read access cycle by said access cycle generator ends, a first address adder for adding the contents of source address register and that of source offset register, the contents of destination address register and that of destination offset register or the contents of pattern address register and that of pattern offset register so as to update the value of each register, and a second address adder for adding the write data of said CPU and the contents of source address register, destination address register or pattern address register so as to update the value of each register;
• and
• (3) access cycle generator means for generating, when receiving a request for reading said VRAM from said CPU, a read access containing at least one of access operations to source, destination and pattern areas by using said drawing address generator and generating, when receiving a request for writing said VRAM from said CPU, a write access or the combination of read access and write access to a destination area by using said drawing address generator and drives said memory controller for said VRAM

A graphic display processing method for reading/writing data inside a video random access memory(VRAM) in accordance with a command from a central processing unit (CPU) and transferring the data, comprising the steps of:

• (a) generating, in place of an access request pursuant to an instruction processing by said CPU, an access request timing for accessing said VRAM for sequential write processings or sequential read and write processings predetermined times;
• (b) when said access request timing is for read processing, generating a read access request containing at least one of requests for accessing a source area of said VRAM which stores data of a transfer originator, a pattern area of said VRAM which stores a pattern and a destination area which is a transfer destination of data;
• (c) when said access request timing is for write to said VRAM, generating either a write access to said destination area or an access request for the combination of read and write for said destination area;
• (d) after performing a first processing operation for holding data of any one of said source area, pattern area and destination area in accordance with the read access request in step (b), updating an address pointer indicating an address of said source area when said source area is accessed and updating an address pointer indicating an address of said pattern area when said pattern area is accessed;
• (e) before writing data subjected to said first processing operation in accordance with the access request in step (c), performing a second processing operation of shifting (inclusive of rotation) or mutual logical operation of the data or the combination thereof;
• and
• (f) after writing the data subjected to said second processing operation to said destination area while inhibiting or permitting writing said VRAM in unit of bit, updating an pointer indicating an address of said destination area.

A graphic display processing apparatus having a central processing unit (CPU), a vide random access memory (VRAM) having a plane structure of one or more planes and adapted to store data, a memory con, roller adapted to generate an access timing for said VRAM, a drawing controller for transferring the data to said VRAM, and a display system comprised of display means, display address generator means for generating a display address for said VRAM, and display controller for generating a display timing for display of the data on said display means, said graphic display processing apparatus comprising:

• sequential transfer sequence means, coupled to said CPU, for generating an access request timing at set times;
• access cycle generator means for expanding the access request timing from said sequential transfer sequence means into one or more accesses and transferring the accesses to said memory controller;
• a data control unit for designating a processing operation of the data on the basis of an instruction from said CPU under the control of said sequential transfer sequence means and access cycle generator means;
• a data operation unit for performing a processing operation of the data to be drawn on said VRAM on the basis of a command from said data control unit under the control of said access circle generator means, said data operation unit is common to a plurality of VRAM's and includes a data structure transformer for transforming the format of the data by using mirror image inversion and swap separately or in combination, a bit mask register for controlling writing to said VRAM in unit of bit, AND means for ANDing the contents of bit mask register and the data of data structure transformer bit by bit, a bit mask shifter for shifting data of said bit mask register, data structure transformer or means, a third merge register for holding the previous contents of data of said data structure transformer, a third shifter for shifting data of said data structure transformer and data of said third merge register, and read data synthesizer means for ORing bits of the contents of read data selector means of each plane so as to synthesize read data supplied to said CPU;
• and
• drawing address generator means for generating a drawing address of the data on the basis of a signal from said access cycle generator means, said drawing address generator means includes a source address register for bolding an address of a source area on said VRAM, a destination address register for holding an address of a destination area a pattern address register for holding an address of a pattern area, a source offset register for holding a value added to the contents of said source address register to update the same when a read access cycle by said access cycle generator ends, a destination offset register for holding a value added to the contents of said destination address register to update the same when a write access cycle by said access cycle generator ends, a pattern offset register for holding a value added to the contents of said pattern address register to update the same when the read access cycle by said access cycle generator ends, a first address adder for adding the contents of source address register and that of source offset register, the contents of destination address register and that of destination offset register or the contents of pattern address register and that of pattern offset register so as to update the value to each register, and a second address adder for adding the write data of said CPU and the contents of source address register, destination address register or pattern address register so as to update the value of each register.