US 5,353,383 AGranted

Neural network circuit

AssigneeNippon Telegraph and Telephone Corporation

InventorsKuniharu Uchimura, Osamu Saito, Yoshihito Amemiya, Atsushi Iwata

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Abstract

A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof being inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients being inputted into an addition circuit and accumulated, and this accumulation result determining the output value. A threshold value circuit determines the final output value, according to a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can include simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients.

A neural network circuit including a plurality of neuron circuits, comprising:

a plurality n of input terminals for receiving input signals, where n is an integer greater than 1;
two weight coefficients corresponding to each of said input terminals;
a first subtraction circuit for calculating a first difference between a larger one of said two weight coefficients and a corresponding input signal;
a first rectification circuit for discriminating and passing only positive value results of said first subtraction circuit;
a first non-linear circuit producing a non-linear output according to results from said first rectification circuit;
a second subtraction circuit for calculating a second difference between a smaller one of said two weight coefficients and a corresponding input signal;
a second rectification circuit for discriminating and passing only positive value results of said second subtraction circuit;
a second non-linear circuit producing a non-linear output according to results from said second rectification circuit;
an addition circuit for adding and accumulating outputs of said first and second non-linear circuits for each of said plurality n of input terminals;
a threshold value circuit having a predetermined threshold value for determining a magnitude of a result of said accumulation in accordance with said predetermined threshold value, and outputting said accumulation result, wherein said neuron circuits use the output results of said threshold value circuit as output signals;
and
means of connecting input and output terminals of said neuron circuits, said neuron circuits having independent said weight coefficients with respect to a plurality of said input signals inputted into each of said network circuits for executing calculations, an output value of at least one of said neuron circuits being an output signal of said network circuit, and said two weight coefficients and a size of said threshold value of said threshold value circuit controlling said network circuit.

9 more elements

Facts

Application

07/909,993Filed 7 Jul 1992 · division

Priority

JP 2-1796659 Jul 1990

Granted

4 Oct 1994

Term ends

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Classification4 codes

G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G06F 18/2453
Relating to the decision surface: non-linear, e.g. polynomial classifier
G06N
AI and machine learning
G06F
Computing and data processing

Abstract

Claims5