Transmission of a clock signal over an asynchronous data channel
AssigneeAT&T Bell Laboratories
InventorWilliam K. Honea
Life of this patent
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Abstract
An input clock signal associated with an input data signal is divided by a predetermined integer N, to form a sub-rate clock signal. The sub-rate clock signal is sampled and transmitted along with the input data over an asynchronous data channel. At the receiver, the resulting sub-rate clock signal is received and coupled to a phase lock loop which generates a recovered clock signal of the same frequency and substantially in phase with the input clock signal.
Claims12
Transmitter apparatus for communicating an input digital data word and an input clock signal over a communication channel at a data word transmission rate which operates asynchronously with respect to said input clock signal, said transmitter comprising
- means for generating said input data word from an input analog signal sampled by said input clock signal, said input clock signal being derived independently of said input analog signal,
- means for dividing said input clock signal by a predetermined integer to obtain a sub-rate frequency clock signal which is less than or equal to one-half of the data word transmission rate of said transmitter and
- means for combining a logic state sample of said sub-rate clock signal together with said input data word to form each data word to be transmitted in a packet data format from said transmitter.
A data communication system including a transmitter and a receiver connected together over a communication channel,
- said transmitter comprising
- means for generating an input data word from an input analog signal sampled by an input clock signal, said input clock signal being derived independently of said input analog signal,
- means for dividing down said input clock signal to obtain a sub-rate frequency clock signal which is substantially below and operates asynchronously to a data word transmission rate of said transmitter and
- means for combining a logic state sample of said sub-rate clock signal together with said input data word to form each data word to be transmitted in a packet data format from said transmitter;
- and
- said receiver comprising
- means for extracting said logic state sample from each of said data words received from said transmitter and
- phase lock loop for generating, from said logic state sample, a recovered clock signal of the same frequency and substantially in phase with said input clock.
A method of operating a transmitter apparatus to communicate an input digital data word and an input clock signal over a communication channel at a data word transmission rate which operates asynchronously with respect to said input clock signal, said method comprising the steps of
- generating said input data word from an input analog signal sampled by said input clock signal, said input clock signal being derived independently of said input analog signal,
- dividing said input clock signal by a predetermined integer to obtain a sub-rate frequency clock signal which is substantially below a data word transmission rate of said transmitter and
- combining a logic state sample of said sub-rate clock signal together with said input data word to form each data word to be transmitted in a packet data format from said transmitter.
A method of operating a data communication system including a transmitter and a receiver connected together over a communication channel, said method, at said transmitter, comprising the steps of
- accepting an input clock signal which is asynchronous with respect to a data word transmission clock of said transmitter,
- generating an input data word from an input analog signal sampled by an input clock signal, said input clock signal being derived independently of said input analog signal,
- dividing down said input clock signal to obtain a sub-rate frequency clock signal which is substantially below and operates asynchronously to a data word transmission rate of said transmitter,
- combining a logic state sample of said sub-rate clock signal together with said input data word to form each data word to be transmitted in a packet data format from said transmitter;
- and
- at said receiver
- extracting said logic state sample from each of said data words received from said transmitter and
- generating, from said logic state sample, a recovered clock signal of the same frequency and substantially in phase with said input clock.
Dependencies are inferred from the claim text.