Intermittenceless switching system

An intermittenceless switching system including a time division switch for providing interconnection between a network communication channel and a plurality of time division multiplex communication channels, comprising:

• a system input connectable to receive data from the plurality of time division multiplex communications channels;
• a system output connectable to transmit data from the system to the network communication channel;
• first and second speech path memories, each having sufficient capacity to store a frame of data comprising a plurality of time slots and each having an input and an output;
• first and second write address change switches connected to said input of said first and second speech path memories respectively;
• first and second read address change switches connected to said output of said first and second speech path memories respectively;
• a memory write switch connected to said system input and said first and second write address change switches to selectively switch data from the system input to one of said first and second write address change switches;
• a memory read switch connected to said first and second read address change switches to selectively connect one of said first and second read address change switches to said system output;
• memory switch control means for continuously alternating the connections established by said memory read switch and said memory write switch so that data is written to said first speech path memory while it is read from said second speech path memory and read from said first speech path memory while it is written to said second speech path memory;
• processing means for generating switch control information specifying desired operation of said first and second read address change switches and said first and second write address change switches;
• buffer memory means connected to said processing means and having a buffer memory means output, for receiving switch control information from said processing means, buffering said switch control information, and transmitting said switch control information to said buffer memory means output in synchronism with a time slot clock;
• and
• connection control means connected to said buffer memory means output, said first and second write address change switches, and said first and second read address change switches, for controlling the operation of said read address change switches and said write address change switches according to said switch control information received from said buffer memory means output.