Word line driving circuit and semiconductor memory device using the same

A semiconductor memory device comprising:

• a memory cell array connected to word lines and bit lines;
• a row address decoder selecting one of the word lines in response to a row address signal;
• a column address decoder selecting one of the bit lines in response to a column address signal;
• and
• data input/output means, coupled to the memory cell array, for writing data into the memory cell array and reading data from the memory cell array,
• said row address decoder comprising word line driving circuits respectively provided for the word lines,
• each of the word line driving circuits comprising:
• a first transistor having a first terminal receiving an input signal based on the row address signal, a second terminal, and a control terminal receiving a first timing signal;
• a second transistor having a first terminal receiving a second timing signal, a second terminal connected to the word line, and a control terminal connected to the second terminal of the first transistor;
• and
• a third transistor having a first terminal connected to the second terminal of the second transistor, a second terminal set at a predetermined potential, and a control terminal receiving a third timing signal,
• the first transistor having a threshold voltage less than that of the third transistor.