Semiconductor dynamic random-access memory device

A semiconductor memory device comprising:

• a plurality of memory cells, each comprising a single MOS transistor and a single capacitor;
• a main bit line pair comprising first and second main bit lines;
• a precharge circuit for precharging each said main bit line to a predetermined potential according to a precharge signal;
• a main sense amplifier for amplifying signals between said paired main bit lines;
• a sub-bit line pair, provided for said main bit line pair, comprising first and second sub-bit lines, said sub-bit line pair being connected to said plurality of memory cells;
• a plurality of word lines for selecting a specified memory cell from among said plurality of memory cells;
• and
• a sub-sense amplifier provided for said sub-bit line pair for amplifying a voltage between said first and second sub-bit lines to provide an amplified voltage to said main bit line pair;
• wherein,
• a word line corresponding to said memory cell is connected to the gate of said MOS transistor;
• and
• some of said memory cells are connected to the first main bit line by said capacitor thereof and connected to the second sub-bit line by said channel of said MOS transistor thereof, and other memory cells are connected to the second main bit line by said capacitor thereof and connected to the first sub-bit line by said channel of said MOS transistor thereof.