Semiconductor memory device

A semiconductor memory device comprising:

• a data input terminal for receiving data for storage;
• an address signal input terminal for receiving an address signal which designates an address at which said data is written and from which said data is read;
• a main memory circuit for receiving said data from said data input terminal and said address signal from said address signal input terminal and for thereafter writing said data at an address which is specified by said address signal or otherwise retrieving said data already stored therein;
• a defective address specifying circuit for outputting defective address specifying information which specifies an address which corresponds to a defective portion of said main memory circuit;
• a detection circuit for receiving said address signal and said defective address specifying information respectively from said address signal input terminal and said defective address specifying circuit, for detecting whether the address specified by said address signal coincides with the address specified by said defective address specifying information, and for outputting a detection signal indicative of a result of the detection;
• a redundancy memory circuit for receiving said detection signal and said data respectively from said detection circuit and said data input terminal and thereafter storing said data of the defective address in response to said detection signal which indicates the coincidence or otherwise outputting said data about the defective address already stored therein;
• and
• a data select circuit for receiving said data which is read from said main memory circuit, said data which is outputted from said redundancy memory circuit and said detection signal from said detection circuit and for selectively outputting said data received frown said main memory circuit or said data received from said redundancy memory circuit, in accordance with said detection signal.