Methods and apparatus for digitally encoding repetitive analog waveforms

Apparatus for encoding a repetitive analog waveform as m n-bit digital words, where m and n are positive integers, the apparatus comprising:

• a sampler for taking analog samples of the repetitive waveform at each of m distinct sampling points, each of the m distinct sampling points having a respective predetermined delay with respect to a reference point on the repetitive waveform, the sampler comprising:
• a clock generator for generating a clock signal at a clock rate;
• a sampling pulse generator for deriving sampling pulses from the clock signal;
• a fine delay element comprising a delay lock loop responsive to a fine delay select code to delay the sampling pulses relative to the clock signal by a fine delay corresponding to the fine delay select code;
• a coarse delay element comprising a counter for counting sampling pulses and a switching arrangement responsive to the counter and a coarse delay select code for selectively passing only delayed sampling pulses having a coarse delay corresponding to the coarse delay select code;
• and
• a processor operable to cycle the fine delay select code and the coarse delay select code such that the delay is cycled through a full range of coarse delay increments before each addition of a fine delay increment;
• and
• an encoder for digitally encoding each sample.

Apparatus for encoding a repetitive analog waveform as m n-bit digital words, where m and n are positive integers, the apparatus comprising:

• a sampler for taking n distinct analog samples of the repetitive waveform at each of m distinct sampling points, each of the m distinct sampling points having a respective predetermined delay with respect to a reference point on the repetitive waveform,the sampler comprising:
• a clock generator for generating a clock signal at a clock rate;
• a sampling pulse generator for deriving sampling pulses from the clock signal;
• a fine delay element responsive to a fine delay select code to delay the sampling pulses relative to the clock signal by a fine delay corresponding to the fine delay select code;
• and
• a processor operable to cycle the fine delay select code;
• and
• an encoder for digitally encoding each sample;
• wherein:
• the fine delay element is responsive to the fine delay select code and the clock signal to generate a modified clock signal having a duty cycle which corresponds to the fine delay select code;
• and
• the sampling pulse generator comprises a frequency multiplier operable to generate sampling pulses at a multiple of the clock rate, the sampling pulses being synchronized to a trailing edge of the modified clock signal.