Master slice semiconductor integrated circuit with output drive current control

A master slice semiconductor integrated circuit which has a row of cells which are a collection of basic cells comprising a plurality of transistors and in which a desired logic circuit is configured with the said basic cells comprising a plurality of transistors and in which said desired logic circuit is configured with the said basic cells by providing a power source line and a signal line on a chip, characterized in that said circuit has first control signal generating means which generates first control signals by performing logical operation according to an output signal of a first circuit of the said logic circuit and a first current value changing signal, a second control signal generating means which generate second control signals by performing logical operation according to an output signal of a second circuit of said logic circuit and a second current value changing signal, a selection control means which actively selects either the first control signal generating means or the second control signal generating means, at least two first current paths which are formed in parallel between a first power source potential and an output terminal and which are opened and closed by the first control signals, and at least two second current paths which are formed in parallel between a second power source potential and said output terminal and which are opened and closed by the second control signals.

A master slice semiconductor integrated circuit comprising:

• a chip;
• a logic circuit formed from a plurality of basic cells composed of a plurality of transistors on said chip, said logic circuit providing an output signal;
• means for providing a current value changing signal;
• a power source line providing a power source potential and an output line with an output terminal on said chip;
• control signal generating means connected to receive the output signal and the current value changing signal for performing a logical operation on the output signal and the current value changing signal in order to produce control signals;
• and
• a current supplying means having at least two current paths connected in parallel between said power source line and said output line, said current supplying means being connected to receive the control signals so that each current path is opened or closed by a respective control signal,
• wherein said current supplying means are formed on said chip and comprise a pair of field effect transistors disposed symmetrically about said output line which is connected to the output terminal, each transistor has a crossunder portion which extends close to and in parallel with the said output line, a plurality of branch gate electrodes which branch from the crossunder portion in a first direction substantially orthogonal to the crossunder portion, a diffusion layer which is formed in self-alignment with a region crossing said branch gate electrodes, and branch source regions and branch drain regions which conductively contact with a pair of regions sandwiching said branch gate electrodes in said diffusion layer, said branch drain regions branch from said output line and are in parallel with said branch gate electrodes, and said branch source electrodes branch from a source common wiring portion in a second direction opposite to the first direction.