Differential comparator circuit

A combination comprising:

• first, second, third, fourth and fifth transistors, each transistor having drain and source electrodes defining the ends of a conduction path and a gate electrode;
• first and second power terminals;
• first and second signal input terminals;
• a signal output terminal;
• means connecting the drain of said first transistor to said first power terminal, its gate to said first signal input terminal and its source to a first node;
• means connecting the drain of said second transistor to said signal output terminal, its gate to said second signal input terminal, and its source to a second node;
• means connecting the conduction path of said third transistor between said first and second nodes;
• means connecting the conduction path of said fourth transistor between said first node and said second power terminal;
• means connecting the conduction path of said fifth transistor between said second node and said second power terminal;
• means for selectively coupling the gate of said fourth transistor to said second node and the gate of said fifth transistor to said first node;
• and
• a terminal connected to the gate electrode of said third transistor for applying a pulsed potential to selectively condition said third transistor to conduct.

A combination comprising:

• first, second, third, fourth and fifth insulated gate field effect transistors (IGFETs), each IGFET having drain and source electrodes defining the ends of a conduction path and a gate electrode;
• first and second power terminals;
• first and second signal input terminals;
• a signal output terminal;
• means connecting the drain of said first IGFET to said first power terminal, its gate to said first signal input terminal and its source to a first node;
• means connecting the drain of said second IGFET to said signal output terminal, its gate to said second signal input terminal, and its source to a second node;
• means connecting the conduction path of said third IGFET between said first and second nodes;
• means connecting the conduction path of said fourth IGFET between said first node and said second power terminal;
• means connecting the Conduction path of said fifth IGFET between said second node and said second power terminal;
• means coupled to the gate of the IGFET for selectively applying a turn-off voltage to the gate of said third IGFET during one period of time and concurrently applying a like valued turn-on voltage to the gates of said first and second IGFETs;
• means for selectively coupling potentials appearing at the first and second nodes to the gate electrodes of the fifth and fourth transistors respectively.

A comparator comprising:

• first and second signal input terminals for applying first and second signals to be compared;
• first, second, third, fourth and fifth insulated gate field effect transistors, each transistor having drain and source electrodes defining the ends of a conduction path and a gate electrode;
• means for serially coupling the conduction paths of the first and second transistors between positive and negative supply terminals, and connecting the gate electrode of the first transistor to said first signal input terminal;
• means for serially coupling the conduction paths of the third and fourth transistors between said positive and negative supply terminals, and connecting the gate electrode of the third transistor to said second signal input terminal;
• means for alternately coupling and decoupling the control electrodes of the second and fourth transistors to an interconnection of the third and fourth transistors and an interconnection of the first and second transistors respectively;
• means for connecting the conduction path of the fifth transistor between the interconnection of the third and fourth transistors and the interconnection of the first and second transistors and applying a potential for selectively conditioning the fifth transistor to conduct when said means for alternately coupling and decoupling is in a decoupling state and an output provided from the third transistor.