US 5,352,936 AGranted

High voltage tolerant voltage pump constructed for a low voltage CMOS process

AssigneeIntel Corporation

InventorMichael J. Allen

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Abstract

An integrated circuit charge pump which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. One of the devices has its body well connected to its drain terminal to provide a diode between the source and body well which allows the device to turn on and off when subject to a series of input pulses at its drain terminal. A third similarly biased N well P channel device is connected in series with the pair of P channel devices to provide the voltage pumping effect at an output terminal. These devices have been found capable of generating voltages levels of ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Claims18

Dependent claims

An integrated circuit charge pump circuit manufactured in a P- substrate material comprising:

a first P channel N well field effect transistor device having source, gate, and drain terminals,
the gate terminal being connected to a first voltage source of a first level,
the source terminal being connected to receive a second voltage of a second level higher than the first level;
a second P channel N well field effect transistor device having source, gate, and drain terminals,
the gate terminal being connected to the N well and the drain terminal of the second P channel N well field effect transistor device,
the source terminal being connected to the drain terminal of the first P channel N well field effect transistor device;
a third P channel N well field effect transistor device having source, gate, and drain terminals,
the gate terminal being connected to the N well and the drain terminal of the third P channel N a well field effect transistor device,
the source terminal being connected to the drain terminal of the second P channel N well field effect transistor device,
the drain terminal being connected to an output circuit having an input capacitance;
and
a source of voltage pulses input at the drain of the second P channel N well field effect transistor device whereby the second voltage at the source terminal of the first P channel N well field effect transistor device is increased by a voltage essentially equal to the voltage pulses and furnished to the output circuit by the third P channel N well field effect transistor.

9 more elements

An integrated circuit charge pump circuit comprising first, second, third, and fourth circuit nodes;

first means for transferring any voltage of a first level from the first node to the second node;
first diode means for providing a voltage at the second node to the third node whenever a voltage level at the second node is greater than a voltage level at the third node;
means for storing a charge at the third node,
second diode means for providing a voltage at the third node to the fourth node whenever a voltage level at the third node is greater than a voltage level at the fourth node;
means for storing a charge at the fourth node, and
means for alternately raising and lowering a level of voltage at the third node to alternately bias the first diode means to cease transferring current when a voltage level is raised and to transfer current when a voltage level is lowered and simultaneously to alteratively bias the second diode means to transfer current when a voltage level is raised and to cease transferring current when a voltage level is low.

3 more elements

An integrated circuit comprising:

a plurality of circuit joined in a circuit and designed to function with source voltage having a first value;
and
a charge pump circuit designed to function with source voltages of a second higher level, the circuit charge pump circuit comprising
first, second, third and fourth circuit nodes;
first means for transferring any voltage of second level from the first node to the second node;
first diode means for providing a voltage at the second node to the third node whenever a voltage level at the second node is greater than the voltage level at the third node;
means for storing a charge at the third node,
second diode means for providing a voltage at the third node to the fourth node whenever a voltage level at the third node is greater than a voltage level at the fourth node;
means for storing a charge at the fourth node;
and
means for alternately raising and lowering a level of voltage at the third node to alternately bias the first diode means to cease transferring current when a voltage level is raised and to transfer current when a voltage level is lowered and simultaneously to alternatively bias the second diode means to transfer current when a voltage level is raised and to cease transferring current when a voltage level is low.

8 more elements

Dependencies are inferred from the claim text.