Method for forming inter-metal dielectrics in a semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Gyu Kim, Ji-Hyun Choi
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Abstract
A method for forming an inter-metal dielectrics in a semiconductor device includes the steps of sequentially forming a first and second insulating layers over a semiconductor substrate with a patterned metal layers, etching-back the second insulating layer so as to form second insulating spacers over the side walls of the first insulating layer, and growing a third insulating layer over the first and second insulating layers, the growing speed of the third insulating layer being different from the region over the first insulating layer to the region over the second insulating layer.
Claims11
A method for forming a planarized dielectric layer on a structure comprised of a semiconductor substrate and a patterned conductive layer formed thereon, whereby the topology of the structure consists of raised surface features defining recesses therebetween, the method comprising the steps of:
- forming a first insulating layer on said structure;
- forming a second insulating layer on said first insulating layer;
- etching back said second insulating layer to remove portions of said second insulating layer disposed on said first insulating layer and above said raised surface features, but without removing any of said first insulating layer, to thereby expose portions of said first insulating layer disposed on said raised surface features and to leave remaining portions of said second insulating layer in said recesses;
- and,
- depositing a third insulating layer on said exposed portions of said first insulating layer at a first deposition rate, and depositing said third insulating layer within said recesses at a second deposition rate, wherein the difference between said first and second deposition rates is such as to result in the upper surface of said third insulating layer having a substantially flat profile.
A method for forming a planarized dielectric layer on a structure comprised of a semiconductor substrate and a patterned conductive layer formed thereon, whereby the topology of the structure consists of a raised surface features defining recesses therebetween, the method comprising the steps of:
- forming a first insulating layer on said structure;
- forming a second insulating layer on said first insulating layer;
- applying a sacrificial layer on said second insulating layer;
- etching back said sacrificial layer to expose portions of said second insulating layer disposed above said raised surface features, thereby leaving remaining portions of said sacrificial layer in said recesses;
- removing said exposed portions of said second insulating layer by using said remaining portions of said sacrificial layer as a mask, to thereby expose portions of said first insulating layer disposed on said raised surface features;
- removing said remaining portions of said sacrificial layer;
- and,
- depositing a third insulating layer on said exposed portions of said first insulating layer at a first deposition rate, and
- depositing said third insulating layer within said recesses at a second deposition rate, wherein the difference between said first and second deposition rates is such as to result int he upper surface of said third insulating layer having a substantially flat profile.
Dependencies are inferred from the claim text.