Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules

A method for attaching at least one semiconductor chip, each with an electrical conductor disposed on an underside thereof, to a substrate having a surface, and having chip wells therein, causing chip attachment, chip alignment, and chip planarization substantially simultaneously, comprising:

• providing on said substrate surface an inner layer of electrical conductor having solder wettability;
• providing on said inner layer an outer layer of an electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip;
• placing a solder preform on each respective one of said at least one window;
• placing a chip on each respective one of said solder preforms;
• placing said substrate into a structure capable of applying isostatic pressure;
• overlaying said substrate and said at least one chip with a dielectric film layer;
• applying pressure over said dielectric film layer;
• and subsequently
• heating said substrate above the melting point of said solder preforms to cause each of said at least one chip to be substantially simultaneously self-aligned within said at least one window and planarized with respect to said surface.