SOI type semiconductor device and manufacturing method therefor

A manufacturing method for a lateral bipolar transistor, comprising:

• the first step of forming a transistor forming region on an upper surface of an insulating substrate;
• the second step of forming a first insulating film on an upper surface of said transistor forming region;
• the third step of forming a first impurity diffusing region on one side of said transistor forming region;
• the fourth step of introducing a second conduction type of impurity into said first impurity diffusing region, and then diffusing said second conduction type of impurity from said first impurity diffusing region into a first portion of said transistor forming region near said first impurity diffusing region to form a base region in said first portion;
• and
• the fifth step of introducing a first conduction type of impurity into said first impurity diffusing region, and then diffusing said first conduction type of impurity from said first impurity diffusing region into a second portion of said transistor forming region between said first portion and said first impurity diffusing region to form an emitter region in said second portion.

A manufacturing method for a lateral bipolar transistor, comprising:

• the first step of forming a transistor forming region of a first conduction type on an upper surface of an insulating substrate:
• the second step of forming a first insulating film on an upper surface of said transistor forming region;
• the third step of forming a first impurity diffusing region on one side of said transistor forming region and forming a second impurity diffusing region on the other side of said transistor forming region;
• the fourth step of forming a second insulating film on a surface of said first impurity diffusing region and forming a third insulating film on a surface of said second impurity diffusing region;
• and
• the fifth step of introducing a second conduction type of impurity into said first impurity diffusing region, then introducing a first conduction type of impurity into said first impurity diffusing region and said second impurity diffusing region, then diffusing said second conduction type of impurity from said first impurity diffusing region into a first portion of said transistor forming region near said first impurity diffusing region to form a base region in said first portion, simultaneously diffusing said first conduction type of impurity from said first impurity diffusing region into a second portion of said transistor forming region between said first portion and said first impurity diffusing region to form an emitter region in said second portion, and simultaneously diffusing said first conduction type of impurity from said second impurity diffusing region into a third portion of said transistor forming region adjacent to said second impurity diffusing region to form a collector contact region in said third portion with a collector region being formed as a remaining portion of said transistor forming region between said first portion and said third portion.

A manufacturing method for a lateral bipolar transistor, comprising:

• the first step of forming a transistor forming region of a first conduction type on an upper surface of an insulating substrate;
• the second step of forming a first insulating film on an upper surface of said transistor forming region;
• the third step of forming a first impurity diffusing region on one side of said transistor forming region and forming a second impurity diffusing region on the other side of said transistor forming region;
• the fourth step of forming a second insulating film on a surface of said first impurity diffusing region and forming a third insulating film on a surface of said second impurity diffusing region;
• the fifth step of introducing a second conduction type of impurity into said first impurity diffusing region and then diffusing said second conduction type of impurity from said first impurity diffusing region into a first portion of said transistor forming region near said first impurity diffusing region to form a base region in said first portion;
• and
• the sixth step of introducing a first conduction type of impurity into said first impurity diffusing region and said second impurity diffusing region, then diffusing said first conduction type of impurity from said first impurity diffusing region into a second portion of said transistor forming region between said first portion and said first impurity diffusing region to form an emitter region in said second portion, and simultaneously diffusing said first conduction type of impurity from said second impurity diffusing region into a third portion of said transistor forming region adjacent to said second impurity diffusing region to form a collector contact region in said third portion with a collector region being formed as a remaining portion of said transistor forming region between said first portion and said third portion.

A manufacturing method for a lateral bipolar transistor, comprising:

• the first step of forming a transistor forming region on an upper surface of an insulating substrate;
• the second step of forming a first insulating film on an upper surface of said transistor forming region;
• the third step of forming a first impurity diffusing region on one side of said transistor forming region and forming a second impurity diffusing region on the other side of said transistor forming region;
• the fourth step of forming a second insulating film on a surface of said first impurity diffusing region and forming a third insulating film on a surface of said second impurity diffusing region in a self-alignment manner:
• and
• the fifth step of diffusing a second conduction type of impurity from said first impurity diffusing region into a first portion of said transistor forming region below a spacing between said second insulating film and said third insulating film to form a base region in said first portion, diffusing a first conduction type of impurity from said first impurity diffusing region into a second portion of said transistor forming region adjacent to said first impurity diffusing region to form an emitter region in said second portion, diffusing said first conduction type of impurity from said second impurity diffusing region into a third portion of said transistor forming region adjacent to said second impurity diffusing region to form a collector contact region in said third portion with a collector region being formed as a remaining portion of said transistor forming region between said first portion and said third portion, forming a base contact portion through said first insulating film in said spacing between said second insulating film and said third insulating film, and forming a base leading electrode in said base contact portion.

A manufacturing method for a bipolar transistor, comprising:

• the first step of forming first and second element isolating regions spaced from each other in a surface layer of a silicon substrate, then forming a first insulating layer on an entire surface where said first and second element isolating regions are formed, and then forming a groove reaching said silicon substrate through said first insulating layer;
• the second step of forming a collector region connected with said silicon substrate in said groove, then forming a collector leading electrode connected with said collector region in said groove, and then forming a second insulating layer on an entire surface where said collector leading electrode is formed;
• the third step of partially removing said silicon substrate to such an extent that said first and second element isolating regions are exposed, and thereby forming a silicon layer from said silicon substrate remaining between said first and second element isolating regions;
• the fourth step of forming an isolating pattern on a portion of said silicon layer over said collector region;
• the fifth step of forming a polysilicon film and an insulating film on an entire surface where said isolating pattern is formed, then forming a graft base region in an upper layer of said silicon layer at a portion thereof adjacent to at least one of said first and second element isolating regions, and then partially removing said insulating film, said polysilicon film and said isolating pattern on a portion of said silicon layer to form an emitter contact portion;
• and
• the sixth step of forming an emitter side wall insulating film on a side wall of said emitter contact portion, then forming a leading electrode forming film in said emitter contact portion, then diffusing an impurity from said leading electrode forming film into the upper layer of said silicon layer to form a base region connected with said graft base region and form an emitter region in an upper layer of said base region, and then forming an emitter leading electrode from said leading electrode forming film.

A manufacturing method for a semiconductor device having a bipolar transistor and a MOS transistor, comprising:

• the first step of forming first, second and third element isolating elements spaced from each other for isolating a bipolar transistor forming region from a MOS transistor forming region in a surface layer of a silicon substrate, then forming a back gate insulating film on an entire surface of said silicon substrate in said MOS transistor forming region, then forming a first insulating layer on an entire surface where said first, second and third element isolating regions are formed, and then forming first and second grooves reaching said silicon substrate through said first insulating layer in said bipolar transistor forming region and said MOS transistor forming region, respectively;
• the second step of forming a collector region connected with said silicon substrate in said first groove, then forming a collector leading electrode connected with said collector region in said first groove and a back gate electrode in said second groove, and then forming a second insulating layer on an entire surface where said first insulating layer is formed;
• the third step of partially removing said silicon substrate to such an extent that said first, second and third element isolating regions are exposed, and thereby forming a first silicon layer from said silicon substrate remaining between said first and second element isolating regions and a second silicon layer from said silicon substrate remaining between said second and third element isolating regions;
• the fourth step of forming an isolating pattern on a portion of said first silicon layer over said collector region and simultaneously forming a gate insulator forming film on an upper surface of said second silicon layer to thereafter form a gate electrode forming film on said gate insulator forming film;
• the fifth step of forming a polysilicon film and an insulating film on an entire surface where said isolating pattern and said gate electrode forming film are formed, then forming a graft base region in an upper layer of said first silicon layer at a portion thereof adjacent to at least one of said first and second element isolating regions, then partially removing said insulating film, said polysilicon film and said isolating pattern on a portion of said first silicon layer to there form an emitter contact portion and a base leading electrode from said polysilicon film, and simultaneously partially removing said insulating film, said polysilicon film, said gate electrode forming film and said gate insulator forming film on a portion of said second silicon layer to thereby form a gate electrode from said polysilicon film and said gate electrode forming film and a gate insulating film from said gate insulator forming film;
• and
• the sixth step of forming an emitter side wall insulating film on a side wall of said emitter contact portion, then forming a leading electrode forming film on an entire surface where said insulating film is formed, then forming a base region connected with said graft base region in the upper layer of said first silicon layer, an emitter region in an upper layer of said base region, and a pair of source and drain regions in said second silicon layer on both sides of said gate electrode, and then forming an emitter leading electrode in said emitter contact portion from said leading electrode forming film and a pair of source and drain leading electrodes respectively connected with said source and drain regions on both sides of said gate electrode from said leading electrode forming film.

A manufacturing method for a bipolar transistor, comprising:

• the first step of forming first and second element isolating regions spaced from each other in a surface layer of a silicon substrate, then forming a first insulating layer on an entire surface where said first and second element isolating regions are formed, and then forming a groove reaching said silicon substrate through said first insulating layer;
• the second step of forming a base leading electrode connected with said silicon substrate in said groove, and then forming a second insulating layer on an entire surface where said base leading electrode is formed:
• the third step of partially removing said silicon substrate to such an extent that said first and second element isolating regions are exposed, and thereby forming a silicon layer from said silicon substrate remaining between said first and second element isolating regions;
• the fourth step of forming an isolating pattern on a portion of said silicon layer over said base leading electrode;
• the fifth step of forming a polysilicon film and an insulating film on an entire surface where said isolating pattern is formed, then forming a collector region in said silicon layer at a portion thereof adjacent to at least one of said first and second element isolating regions, and then partially removing said insulating film, said polysilicon film and said isolating pattern on a portion of said silicon layer to form an emitter contact portion;
• and
• the sixth step of forming an emitter side wall insulating film on a side wall of said emitter contact portion, then forming a leading electrode forming film in said emitter contact portion, then diffusing an impurity from said leading electrode forming film into said silicon layer to form a base region connected with said base leading electrode and form an emitter region in an upper layer of said base region, and then forming an emitter leading electrode from said leading electrode forming film.

A manufacturing method for a semiconductor device having a bipolar transistor and a MOS transistor, comprising:

• the first step of forming first, second and third element isolating elements spaced from each other for isolating a bipolar transistor forming region from a MOS transistor forming region in a surface layer of a silicon substrate, then forming a back gate insulating film on an entire surface of said silicon substrate in said MOS transistor forming region, then forming a first insulating layer on an entire surface where said first, second and third element isolating regions are formed, and then forming first and second grooves reaching said silicon substrate through said first insulating layer in said bipolar transistor forming region and said MOS transistor forming region, respectively;
• the second step of forming a base leading electrode connected with said silicon substrate in said first groove and a back gate electrode in said second groove, and then forming a second insulating layer on an entire surface where said first insulating layer is formed;
• the third step of partially removing said silicon substrate to such an extent that said first, second and third element isolating regions are exposed, and thereby forming a first silicon layer from said silicon substrate remaining between said first and second element isolating regions and a second silicon layer from said silicon substrate remaining between said second and third element isolating regions;
• the fourth step of forming an isolating pattern on a portion of said first silicon layer over said base leading electrode and simultaneously forming a gate insulator forming film on an upper surface of said second silicon layer to thereafter form a gate electrode forming film on said gate insulator forming film;
• the fifth step of forming a polysilicon film and an insulating film on an entire surface where said isolating pattern and said gate electrode forming film are formed, then forming a collector region in said first silicon layer at a portion thereof adjacent to at least one of said first and second element isolating regions, then partially removing said insulating film, said polysilicon film and said isolating pattern on a portion of said first silicon layer to there form an emitter contact portion and a collector leading electrode from said polysilicon film, and simultaneously partially removing said insulating film, said polysilicon film, said gate electrode forming film and said gate insulator forming film on a portion of said second silicon layer to thereby form a gate electrode from said polysilicon film and said gate electrode forming film and a gate insulating film from said gate insulator forming film;
• and
• the sixth step of forming an emitter side wall insulating film on a side wall of said emitter contact portion and a gate side wall insulating film on a side wall of said gate electrode, then forming a leading electrode forming film on an entire surface where said insulating film is formed, then forming a base region in said first silicon layer, an emitter region in an upper layer of said base region, and a pair of source and drain regions in said second silicon layer on both sides of said gate electrode, and then forming an emitter leading electrode in said emitter contact portion from said leading electrode forming film and a pair of source and drain leading electrodes respectively connected with said source and drain regions on both sides of said gate electrode from said leading electrode forming film.

A manufacturing method for a semiconductor device having a bipolar transistor and a MOS transistor, comprising:

• the first step of forming a back gate insulating film on a silicon substrate in a MOS transistor forming region, then forming a first insulating layer on said silicon substrate, and then forming first and second grooves through said first insulating layer in a bipolar transistor forming region and said MOS transistor forming region, respectively;
• the second step of forming a monosilicon layer in said first groove, then forming first and second polysilicon layers in said first and second grooves to simultaneously form a base leading electrode and a back gate electrode, respectively, and then forming a second insulating layer on said first insulating layer;
• the third step of bonding a back wafer to said second insulating layer, then polishing said silicon substrate to form first and second silicon layers in said bipolar transistor forming region and said MOS transistor forming region, respectively;
• the fourth step of forming a gate insulating film on said first and second silicon layers, then forming third and fourth polysilicon layers on said gate insulating film over said first and silicon layers, respectively, then forming a collector region in said first silicon layer, then forming a collector leading electrode and a gate electrode from said third and fourth polysilicon layers, respectively, then forming a base region in said first silicon layer and source and drain regions in said second silicon layer by diffusion of an impurity from said third and fourth polysilicon layers, respectively, and then forming an emitter region in an upper layer of said base region by diffusion of an impurity from said third polysilicon layer.