US 5,352,621 A · Method for manufacturing an internally shielded dynamic random access memory cell

Abstract

In the manufacturing process of a Dynamic Random Access Memory cell, the conducting layer used for preventing the capacitive coupling between a bit line and a word line is formed over the surface of the entire memory cell excepting the contact legion of a bit line and a storage electrode. Moreover, as the conducting layer used for preventing the capacitive coupling is used as an etching barrier in the etching process forming a contact hole, self-aligned contacts are formed. Therefore, the operation of the unwanted cell of a Dynamic Random Access Memory cell caused by the capacitive coupling is protected and a highly integrated Dynamic Random Access Memory cell is manufactured.

Claims6

Dependent claims

A method for manufacturing an internally shielded Dynamic Random Access Memory cell comprising the steps of:

forming vertically a word line conductively isolated from a silicon substrate;
forming a first insulating layer on said word line;
forming an electrically conducting layer used for preventing the capacitive coupling of said word line and a bit line on said first insulating layer, said conducting layer being conductively isolated from said word line;
forming a second insulating layer used for forming an even surface on said conducting layer;
forming horizontally said bit line conductively isolated from said conducting layer and electrically coupled to a section of said silicon substrate the conductivity of which depends upon a voltage applied to said word line;
and
forming a storage electrode electrically coupled to said section of said silicon substrate, said storage electrode being conductively isolated from said conducting layer.

4 more elements

A method for manufacturing an internally shielded Dynamic Random Access Memory cell comprising the steps of:

forming a field oxide layer in the non-active region of a silicon substrate;
forming a MOSFET having a gate oxide layer, a word line and a source/drain;
forming a first insulating layer over the entire surface;
forming an electrically conducting layer used for preventing the capacitive coupling of said word line and a bit line and a second insulating layer used for forming an even surface on said first insulating layer, said conducting layer being conductively isolated from said word line;
forming a contact hole by etching said second insulating layer, said conducting layer and said first insulating layer in the region of a bit line contact until said source of said MOSFET is exposed;
forming an insulating spacer on the sidewall of said exposed conducting layer;
forming said bit line electrically coupled to said source, said bit line being conductively isolated from said conducting layer;
forming a third insulating layer used for forming an even surface over the entire surface;
forming a contact hole by etching said third insulating layer, said second insulating layer, said conducting layer and said first insulating layer in the contact region of a storage electrode until said drain is exposed;
forming an insulating spacer on the sidewall of said exposed conducting layer;
and
forming a storage electrode electrically coupled to said drain, said storage electrode being conductively isolated from said conducting layer.

9 more elements

Dependencies are inferred from the claim text.

Method for manufacturing an internally shielded dynamic random access memory cell

Life of this patent

Method for manufacturing an internally shielded dynamic random access memory cell

Life of this patent

Abstract

Claims6