Authenticator circuit
AssigneeThe United States of America as represented by the Director, National Security Agency
InventorRonald M. Benincasa
Life of this patent
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Abstract
An authenticator circuit and message authentication apparatus. The circuit includes a plurality of shift register stages, some of which are separated by adders having an input from a succeeding stage. Switching circuits selectively control the second adder inputs to determine the shifting sequence of information passing through the register stages. A message authentication apparatus includes a key generator and authenticator circuit converted at the output of a transmitter. The input of a receiver includes a similar authenticator circuit and key generator, plus a counter.
Claims7
An apparatus, comprising:
- a plurality of delay stages connected to form a shift register;
- a first mod-2 adder inserted between two consecutive stages of said register, the output of the preceeding stage forming one input of said adder and the output of the adder forming the input to the succeeding stage;
- a first terminal for providing information to said apparatus;
- a second terminal for providing information to said apparatus;
- a second mod-2 adder having an input from said first terminal, an input from the last stage of said register, and an output connected to the first stage of said register;
- means controlled by data provided on said second terminal for selectively switching either the information in the last delay stage or a zero to the second input of said first adder;
- and
- an output terminal connected to a selected one of said register stages.
Dependencies are inferred from the claim text.