Digital serial loop filter for high speed control systems

A digital serial programmable loop filter for high frequency control systems comprising:

• an input terminal adapted to receive a serial digital input signal carrying loop error information;
• a serial digital signal processor coupled to said input terminal for filtering said input signal by processing pulse densities of said input signal;
• an output terminal coupled to said processor for carrying a serial output signal representing the filtered value of said serial input signal;
• and
• means coupled to said serial digital signal processor for adjusting a configuration of said filter to at least an open loop and closed loop configuration.

A digital serial loop filter for high frequency control systems comprising:

• an input terminal adapted to receive a serial digital input signal carrying loop error information;
• a serial digital signal processor coupled to said input terminal for filtering said input signal by processing pulse densities of said input signal;
• an output terminal coupled to said processor for carrying a serial output signal representing the filtered value of said serial input signal;
• and
• parallel ports coupled to said serial digital signal processor for interfacing with a microprocessor, said microprocessor programmed to configure said loop.

A digital serial loop filter for high frequency control systems comprising:

• an input terminal adapted to receive a serial digital input signal carrying loop error information;
• a serial digital signal processor, having a proportional path and an integral path, coupled to said input terminal for filtering said input signal by processing pulse densities of said input signal;
• and
• an output terminal coupled to said processor for carrying a serial output signal representing the filtered value of said serial input signal,
• wherein said proportional path is placed in front of said integral path whereby a damping factor of said loop is proportional to about a ratio of a transfer function of said proportional path to a transfer function of said integral path,
• and where n said serial digital signal processor adjusts scaling factors of said proportional path and said integral path substantially linearly.

A digital serial loop filter for high frequency control systems comprising:

• an input terminal adapted to receive a serial digital input signal carrying loop error information;
• a serial digital signal processor coupled to said input terminal for filtering said input signal by processing pulse densities of said input signal, said processor comprising:
• (i) a proportional path;
• (ii) an integral path;
• and
• (iii) a time slot sequencer coupled to said proportional and integral paths to time multiplex at least two proportional and two integral serial signals onto two outputs;
• and
• an output terminal coupled to said processor for carrying a serial output signal representing the filtered value of said serial input signal.

A high frequency Phase-Locked Loop (PLL) comprising:

• a receiver circuit with an input and an output, for receipt of a high frequency digital input signal;
• a phase detector having a first input for receipt of said input signal via said receiver circuit output, and a second input for receipt of a loop clock signal, said phase detector determining a phase error value between said input signal and said loop clock signal and transmitting said phase error value on a first and a second output terminal;
• a phase error processor having two outputs and two inputs for receiving said phase error value from said phase detector outputs, and transforming said phase error value into two serial signals ready for digital filtering;
• a digital serial loop filter with programmable loop variables having two inputs to receive said phase error processor outputs and two outputs, for filtering said serial signals by processing a pulse densities of said serial signals and an acquisition time controller to automatically adjust acquisition speed of the PLL;
• a phase to frequency converter having two inputs for receiving said digital serial loop filter outputs, said phase to frequency converter generating a frequency based signal from said filter output signals at an output;
• an oscillator circuit for generating a local reference clock signal;
• a frequency controlled oscillator for receiving said phase to frequency converter output and said local clock signal and generating said loop clock signal;
• and
• an input/output controller facilitating an interface between a microprocessor and said digital loop filter, said phase to frequency converter, and said acquisition speed controller via a multi-bit bidirectional bus.

A digital serial loop filter for high frequency, second order phase-locked loop (PLL) applications comprising:

• a proportional path including a digital scaler with two inputs and two outputs, for scaling pulse densities of a serial input signal;
• an integral path including a digital integrator having two inputs coupled to said digital scaler outputs, and a plurality of outputs;
• a multi-bit pulse density modulator to convert said plurality of digital integrator outputs to a single serial signal;
• a smoothing circuit to convert said single serial signal generated by said pulse density modulator into two signals compatible to said scaler outputs;
• a multiplexer for time-multiplexing two outputs of the filter between said digital scaler outputs and said smoothing circuit outputs;
• and
• a 2-bit counter for generating 4-time-slot sequences to control said multiplexer.