Dynamic random access memory device having a transfer circuit for coupling a sense amplifier circuit with an accessed cell and a plate line

A dynamic random access memory device fabricated on a semiconductor chip, comprising:

• a) a plurality of memory cells arranged in rows and columns, and respectively fabricated from storage capacitors respectively coupled in series with first switching transistors, every two columns of memory cells forming a column pair so that said columns of said plurality of memory cells are divided into a plurality of column pairs;
• b) a plurality of bit lines respectively associated with said columns of said plurality of memory cells, each of said plurality of bit lines being coupled with drain nodes of said respective first switching transistors of the associated column, every two adjacent bit lines being paired with each other for forming a plurality of bit line pairs;
• c) a plurality of plate lines respectively associated with said plurality of column pairs and with said plurality of bit line pairs, each of said plurality of plate lines being coupled with counter electrodes of said storage capacitors of the associated column pair;
• d) a plurality of word lines respectively associated with said rows of said plurality of memory cells, each of said plurality of word lines being coupled with gate electrodes of said first switching transistors of the associated row for selectively coupling said storage capacitors with the associated bit lines at a first timing;
• e) a precharging means operative to supply a middle voltage level between a high voltage level and a low voltage level to said plurality of bit lines and to said plurality of plate lines at a second timing before said first timing;
• f) a plurality of sense amplifier circuits respectively associated with said plurality of column pairs, and operative to develop small differential voltages on said respective bit line pairs at a third timing after said first timing;
• and
• g) a plurality of transfer circuits respectively coupled between said plurality of bit line pairs and input node pairs of said respective plurality of senses amplifier circuits, each of said plurality of transfer circuits having a first transfer gate responsive to a first timing signal for coupling one of the bit lines of the associated bit line pair with one of the input nodes of the associated input node pair, a second transfer gate responsive to a second timing signal for coupling the other of said bit lines with the other of said associated input nodes, a third transfer gate responsive to a third timing signal for coupling the associated plate line with said one of said input nodes, and a fourth transfer gate responsive to a fourth timing signal for coupling said associated plate line with said other of said input nodes, said first and fourth timing signals being produced when said plurality of word lines couple one of the storage capacitors with said one of said bit lines between said second timing and said first timing, said second and third timing signals being produced between said second timing and said first timing when said plurality of word lines couple one of the storage capacitors with said other of said bit lines.