Integrated semiconductor memory device utilizing a test circuit

Abstract

A semiconductor memory device of the type having a test circuit incorporated integrally therewith generates test data to be batch written into the device's memory cells. The memory device includes at least one memory block to which there may be connected sense amplifiers through which read/write operations can be effected. A test circuit is also provided which function is to test each memory block. A peripheral circuit is formed electrically connected to any memory blocks. Accordingly, memory blocks as well as the peripheral circuit are formed on a semiconductor substrate onto which there is formed a `single` layer having both high (undoped thin poly-Si current paths-108CH) and low (doped thin poly-Si joint path-108SD) resistivity regions therein. The inherent properties of the undoped high-resistivity current paths 108 CH are such that in response to control signals from control gate electrodes, an electrical conductance of the current paths can be altered. The resultant structure yields improvements in manufacturing costs, test time and ancillary costs associated with memory block testing.

Dependencies are inferred from the claim text.