Serially accessible semiconductor memory with multiple level storage cells

A semiconductor memory comprising:

• a memory cell array including memory cells arranged in a matrix having row lines and column lines, each of the memory cells being connected to one of the row lines and one of the column lines, and each of the memory cells storing a potential corresponding to 4-level data, wherein the memory cells connected to a selected row line simultaneously output the potentials to the corresponding column lines when the selected row line is selected;
• an amplifier circuit connected to the memory cell array, the amplifier circuit including at least three sense amplifiers, each of the sense amplifiers being connected in parallel to one of the column lines, each of the sense amplifiers detecting the potential read from one of the memory cells in accordance with different reference potentials supplied to respective sense amplifiers in data read access, and each of the sense amplifiers supplied with one of the potentials corresponding to the 4-level data in data write access;
• a data converter connected to the amplifier circuit, the data converter converting potentials output from each of the sense amplifiers into data having a plurality of bits in data read access, and selecting one of the at least three sense amplifiers in accordance with write data having two bits in data write access, the selected sense amplifier supplying the potential to the respective column line;
• and
• an input/output circuit connected to the data converter, the input/output circuit serially outputting data supplied from the data converter in data read access and supplying external write data to the data converter in data write access.

A semiconductor device comprising:

• a first memory cell array including memory cells arranged in a matrix having row lines and column lines, each of the memory cells being connected to one of the row lines and one of the column lines, and each of the memory cells storing a potential corresponding to multi-level data having at least two bits;
• a second memory cell array including memory cells arranged in a matrix form having the row lines and the column lines, each of the memory cells being connected to one of the row lines and one of the column lines, each of the memory cells storing a potential as check data corresponding to the multi-level data;
• a row address decoder connected to the second memory cell array, the row address decoder selecting one of the row lines of the first and second memory cell arrays in accordance with address data;
• an amplifier circuit connected to the first and second memory cell arrays, the amplifier circuit including a plurality of sense amplifiers., at least two of said sense amplifiers being connected in parallel to one of said column lines, the sense amplifiers detecting the potential read from the memory cells in accordance with different reference potentials supplied to respective sense amplifiers in data read access, each of the sense amplifiers supplied with one of the potentials corresponding to the multi-level data in data write access;
• a data converter connected to the amplifier circuit, the data converter converting potentials output from the sense amplifiers into data having a plurality of bits in data read access and selecting one of the sense amplifiers in accordance with write data having a plurality of bits in data write access, the selected sense amplifier supplying the potential to the memory cell through the respective column line;
• and
• an input/output circuit connected to the data converter, the input/output circuit serially outputting data, including check data, supplied from the data converter in data read access and supplying external write data to the data converter in data write access;
• wherein the first memory cell array is on a semiconductor substrate, and the second memory cell array is on the semiconductor substrate.

A semiconductor memory device comprising:

• a first memory cell array including memory cells arranged in a matrix having row lines and column lines, each of the memory cells being connected to one of the row lines and one of the column lines, each of the memory cells storing a potential corresponding to 4-level data having at least two bits;
• a second memory cell array including memory cells arranged in a matrix having the row lines and the column lines, each of the memory cells being connected to one of the row lines and one of the column lines, each of the memory cells storing a potential as check data corresponding to the 4-level data;
• a row address decoder connected to the second memory cell array, the row address decoder selecting one of the lines of the first and second memory cell arrays in accordance with address data;
• an amplifier circuit connected to the first and second memory cell arrays, the amplifier circuit including at least three sense amplifiers, each of the sense amplifiers being connected in parallel to one of said column lines, each of the sense amplifiers detecting the level of the potential read from the memory cells in accordance with different reference potentials supplied to respective sense amplifiers in data read access, each of the sense amplifiers being supplied with one of a plurality of potentials corresponding to the 4-level data in data write access;
• a data converter connected to the amplifier circuit, the data converter converting potentials output from the sense amplifiers into data having a plurality of bits in data read access and selecting one of the at least three sense amplifiers in accordance with write data having a plurality of bits in data write access, the selected sense amplifier supplying the potential to the memory cell through the respective column line;
• and
• an input/output circuit connected to the data converter, the input/output circuit serially outputting data including check data supplied from the data converter in data read access and supplying external write data to the data converter in data write access;
• wherein the first memory cell array is on a semiconductor substrate, and the second memory cell array is on the semiconductor substrate.