Method and apparatus for designing the layout of a subcircuit in an integrated circuit

A computer implemented method for designing the layout of a random access memory on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the random access memory including internal cells, such as one or more sense amplifiers, internal buffers and power rails, the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the method comprising the steps of:

• a. establishing the constraints among the layers of circuit features that are determined by the specified process technology;
• b. creating a description of a layout geometry for the random access memory according to the constraints;
• c. using a computer to generate one or more simulation models for the described layout geometry;
• and
• d. using a computer to generate a connectivity test model for the described layout geometry.

A computer based apparatus for designing the layout of a subcircuit on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the subcircuit including internal cells and the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the apparatus comprising:

• means for electronically inputting into a computer the circuit feature positions, a plurality of variables, each variable functionally corresponding to a constraint among the layers of circuit features, and a plurality of constants, each constant corresponding to a specific value for one of the variables;
• memory storage means operatively associated with the means for electronically inputting for storing descriptions of the circuit feature positions, the plurality of variables, and the plurality of constants;
• and
• computer processing means operatively associated with the means for electronically inputting and the memory storage means for establishing the constraints that are determined by the specified process technology, for creating a layout geometry for the subcircuit according to the constraints, for generating one or more simulation models for the described layout geometry and for generating a connectivity test model for the described layout geometry.