Active matrix substrate device and related method

A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of:

• applying first pulses to gates of said n-type transistors;
• applying second pulses to gates of said p-type transistors;
• and
• providing a different in pulse width between said first pulses and said second pulses;
• wherein a first pulse and a second pulse are respectively applied to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode.

A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of:

• applying first pulses to gates of said n-type transistors;
• applying second pulses to gates of said p-type transistors;
• and
• providing a difference in pulse height between said first pulses and said second pulses;
• wherein a first pulse and a second pulse are respectively applied to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode.

An apparatus comprising:

• an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair;
• first feeding means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in one field interval;
• second feeding means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said one field interval;
• and
• phase difference means for providing a difference in phase between the first pulse and the second pulse.

An apparatus comprising:

• an active matrix substrate having pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel-corresponding electrode via the pair;
• first means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in a given interval;
• second means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval;
• and
• means for providing a difference in pulse width between the first pulse and the second pulse;
• wherein said first and second means include means for respectively applying a first pulse and a second pulse to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode.

An apparatus comprising:

• an active matrix substrate having pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel-corresponding electrode via the pair;
• first means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in a given interval;
• second means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval;
• and
• means for providing a different in pulse height between the first pulse and the second pulse;
• wherein said first and second means include means for respectively applying a first pulse and a second pulse to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode.

An apparatus comprising:

• an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair;
• first feeding means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in a given interval;
• second feeding means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval;
• and
• phase difference means for providing a difference in phase between the first pulse and the second pulse, wherein said first and second means include means for respectively applying both a first pulse and a second pulse to respective gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during access to said pixel-corresponding electrode.

A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of:

• applying first pulses to gates of said n-type transistors;
• applying second pulses to gates of said p-type transistors;
• and
• providing a difference in phase between said first pulses and said second pulses, wherein said steps of applying said first and second pulses comprises respectively applying both a first pulse and a second pulse to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during access to said pixel-corresponding electrode.

An apparatus comprising:

• an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair;
• first means for applying a first sequence of pulses to gates of n-type switching transistors of said pairs contained in a common row of the matrix in one field interval;
• second means for applying a second sequence of pulses to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said one field interval;
• and
• timing means for providing a timing difference between the first and second sequences of pulses for reducing DC offset in pixel-corresponding electrodes connected to said pairs contained in said common row of the matrix.

An apparatus comprising:

• an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair;
• first means for applying a first sequence of pulses to gates of n-type switching transistors of said pairs contained in a common row of the matrix in a given interval;
• second means for applying a second sequence of pulses to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval;
• and
• timing means for providing a timing difference between the first and second sequences of pulses for reducing DC offset in pixel-corresponding electrodes connected to said pairs contained in said common row of the matrix, wherein said timing means comprises phase means for applying both said first and sequences of pulses to both said n-type and p-type transistors of a pair when a related pixel-corresponding electrode is being accessed and for causing alternate ones of said first sequence of pulses to precede corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix, and for causing remaining ones of said first sequence of pulses to follow corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix.

An apparatus comprising:

• an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistors, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair;
• first means for applying a first sequence of pulses to gates of n-type switching transistors of said pairs contained in a common row of the matrix in a given interval;
• second means for applying a second sequence of pulses to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval;
• and
• timing means for providing a timing difference between the first and second sequences of pulses for reducing DC offset in pixel-corresponding electrodes connected to said pairs contained in said common row of the matrix, wherein said timing means comprises pulse-width control means for applying both said first and sequences of pulses to both said n-type and p-type transistors of a pair when a related pixel-corresponding electrode is being accessed and for causing alternate ones of said first sequence of pulses to terminate before termination of corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix, and for causing remaining ones of said first sequence of pulses to terminate after termination of corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix.