Image display apparatus for displaying images of a plurality of kinds of video signals with asynchronous synchronizing signals and a timing correction circuit

A television set comprising:

• a tuner means for respectively converting broadcast waves modulated according to a plurality of kinds of video signals into said plurality of kinds of video signals;
• a switch means for selecting one of said plurality of kinds of video signals and for outputting a selected video signal;
• a first synchronizing signal generating means for reproducing and generating first vertical and horizontal synchronizing signals in response to said selected video signal outputted from said switch means, said selected video signal of one frame being composed of an odd field and an even field each field including a plurality of scanning lines;
• a second synchronizing signal generating means for generating second vertical and horizontal synchronizing signals for deflection of a display so that said generated second vertical and horizontal signals are respectively asynchronous with said vertical and horizontal synchronizing signals generated by said first synchronizing signal generating means;
• a display means for displaying an image of said selected video signal thereon with a predetermined field frequency and a predetermined number of scanning lines, said display means being controlled by a deflection which is responsive to said second vertical and horizontal synchronizing signals outputted from said second synchronizing signal generating means;
• a first converting means for converting said selected video signal, having a first field frequency which is lower than said predetermined field frequency and having said predetermined number of scanning lines, into an output second video signal having said predetermined field frequency and said predetermined number of scanning lines, using said first and second vertical and horizontal synchronizing signals generated by said first and second synchronizing signal generating means, and for outputting said output second video signal to said display means;
• and
• a second converting means for converting another selected video signal, having a first number of scanning lines which is smaller than said predetermined number of scanning lines and having said predetermined field frequency, into an output fourth video signal having said predetermined field frequency and said predetermined number of scanning lines, using said first and second vertical and horizontal synchronizing signals generated by said first and second synchronizing signal generating means, and for outputting said output fourth video signal to said display means;
• wherein said switch means enables one of said first and second converting means to operate depending on said selected video signal.

A video signal converter apparatus comprising:

• a first converting means for converting an inputted first video signal, having a first field frequency which is lower than a predetermined field frequency and having a predetermined number of scanning lines, into an output second video signal having said predetermined field frequency and said predetermined number of scanning lines, using external first and second vertical and horizontal synchronizing signals, said first vertical and horizontal synchronizing signal being respectively asynchronous with said second vertical and horizontal synchronizing signals, and for outputting said output second video signal, said inputted first video signal of one frame being composed of an odd field and an even field each field including a plurality of scanning lines;
• said first converting means comprising:
• first and second field memories each memory storing said inputted first video signal of one field;
• a first judgment signal generating means for judging whether or not the scanning lines of the odd field have been replaced by the scanning lines of the even field when displaying the image of said inputted first video signal on display means, and for generating a first judgement signal for representing the judgement result;
• a first control signal generating means for generating a first write control signal for controlling said first and second field memories alternately by one field of said inputted first video signal to write said inputted first video signal therein and a first read control signal for controlling said first and second field memories to read out said first video signal as said output second video signal therefrom in response to said external first and second vertical and horizontal synchronizing signals, and for outputting the first write and read control signals to said first and second field memories, said first control signal generating means delaying said first read control signal by one scanning line in response to said first judgement signal representing that the scanning lines of the odd field have been replaced by the scanning lines of the even field;
• and
• a timing correction means for delaying said first read control signal by one scanning line in response to said first judgement signal representing that the scanning lines of the odd field have been replaced by the scanning lines of the even field, thereby preventing said first read control signal from being generated prior to said first write control signal, and thereby preventing said first write control signal from being generated prior to said first read control signal.

A video signal converter apparatus comprising:

• a second converting means for converting an inputted third video signal, having a first number of scanning lines which is smaller than a predetermined number of scanning lines and having a predetermined field frequency, into an output fourth video signal having said predetermined field frequency and said predetermined number of scanning lines, using external first and second vertical and horizontal synchronizing signals, said first vertical and horizontal synchronizing signals being respectively asynchronous with said second vertical and horizontal synchronizing signals, and outputting said output fourth video signal, an inputted third video signal of one frame being composed of an odd field and an even field each field including a plurality of scanning lines;
• said second converting means comprising:
• first and second field memories each memory storing said inputted third video signal of one field;
• a delay means for delaying said third video signal outputted from said first and second field memories by one scanning line;
• a second control signal generating means for generating a second write control signal for controlling said first and second field memories to write said inputted third video signal therein and a second read control signal for controlling said first and second field memories to read out said third video signal therefrom so as to insert a predetermined video signal of one field having no data into said read-out third video signal for a predetermined time interval in response to said external first and second vertical and horizontal synchronizing signals, and for outputting the second write and read control signals to said first and second field memories, the frequency of the second read control signal being set to be higher than that of the second write control signal depending on a ratio of the frequency of the read control signal to the frequency of the write control signal;
• a first amplifying means for amplifying said third video signal outputted from said first and second field memory by a predetermined first amplification factor;
• a second amplifying means for amplifying said third video signal outputted from said delay means;
• an adding means for adding said third video signal amplified by said first amplifying means and said third video signal amplified by said second amplifying means so as to interpolate said predetermined video signal of one field having no data in the added video signal, and for outputting the added video signal having the addition result as said output fourth video signal;
• a further judgment signal generating means for judging whether or not the scanning lines of the odd field have been replaced by the scanning lines of the even field when displaying the image of said inputted third video signal on display means, and for generating a further judgement signal for representing the judgement result;
• and
• a timing correction means for delaying said second read control signal by one scanning line in response to said further judgment signal representing that the scanning lines of the odd field have been replaced by the scanning lines of the even field, thereby preventing said second read control signal from being generated prior to said second write control signal, and thereby preventing said second write control signal from being generated prior to said second read control signal.