Method of cancelling offset errors in phase detectors

A phase detector circuit for comparing the phase of first and second input signals, comprising:

• first fixed delay means responsive to the first input signal for producing a fixedly delayed first signal which is a replica of the first input signal and delayed relative thereto by a fixed delay;
• second fixed delay means responsive to the second input signal for producing a fixedly delayed second signal which is a replica of the second input signal and delayed relative thereto by the fixed delay;
• controlled delay means responsive to the second input signal for producing a controllably delayed second signal which is a replica of the second input signal and delayed relative thereto by a controlled delay;
• a first phase detector responsive to said fixedly delayed first signal and said adjustably delayed second signal for providing a first phase detector output that comprises the output of the phase detector circuit;
• a second phase detector responsive to said fixedly delayed second signal and said adjustably delayed second signal for providing a second phase detector output, said first and second phase detectors having substantially identical respective offset errors;
• and
• control means responsive to said second phase detector output for controlling said controlled delay means to set said controlled delay such that said second phase detector output indicates zero phase error;
• whereby said controlled delay compensates the offset error of said first phase detector.