Sample and hold circuit with push-pull output charging current

A sample and hold circuit comprising:

• a load dependent current source,
• an input terminal,
• an output terminal,
• a sampling gate comprising a pair of input transistors connected to receive an input voltage signal at said input terminal and a pair of output transistors connected to provide to said output terminal (a) an output voltage signal which tracks said input signal, and (b) a current from said load dependent current source, and
• a control circuit that actuates said input and output transistors during a track mode and deactuates said input and output transistors during a hold mode, said control circuit including a pair of bias current sources, means for directing the bias current source currents through respective input transistors during a track mode, means for diverting said bias current source currents away from said input transistors during a hold mode, a pair of diode circuits connected to said sampling gate to complete respective circuit paths for said diverted currents during a hold mode, and a bootstrap circuit interconnecting said output terminal with said diode circuits to provide a diode circuit bias voltage that tracks the sampling gate output voltage, said diode circuits being configured to reverse bias said input transistors during a hold mode in response to said bias voltage.

A sample and hold circuit, comprising:

• a load dependent current source,
• an input terminal,
• an output terminal,
• a sampling gate comprising a pair of input transistors connected to receive an input voltage signal at said input terminal and a pair of output transistors connected to provide to said output terminal (a) an output voltage signal which tracks said input signal, and (b) a current from said load dependent current source, and
• a control circuit that actuates said input and output transistors during a track mode and deactuates said input and output transistors during a hold mode, said control circuit comprising first and second bias current sources, first and second pairs of differentially connected transistors, the first transistors of said first and second differential pairs connected to complete current paths for respective input transistors and bias current sources, the second transistors of said first and second differential pairs connected to divert said bias current source currents away from said input transistors, and a driver circuit connected to actuate the first transistors of said differential pairs during a track mode and the second transistors of said differential pairs during a hold mode,
• said driver circuit comprising third and fourth pairs of differentially connected transistors connected to provide alternating actuating signals for the transistors of said first and second differential pairs, respectively, in response to input clock signals, the transistors of said first, second, third and fourth differential pairs comprising common-type bipolar transistors within each pair of type-npn or type-pnp, the transistors of said first differential pair being of opposite type to the transistors of said third differential pair, and the transistors of said second differential pair being of opposite type to the transistors of said fourth differential pair.

A sample and hold circuit for applying output signals to an output terminal to which a signal holding means can be connected, comprising:

• positive and negative voltage buses,
• an input terminal,
• an output terminal,
• first and second bias current sources respectively receiving current from said positive voltage bus and delivering current to said negative voltage bus,
• a pnp input transistor having its base connected to said input terminal, its emitter connected to receive current from said first bias current source, and its collector connected to a negative voltage bus,
• an npn input transistor having its base connected to said input terminal, its emitter connected to deliver current to said second bias current source, and it collector connected to a positive voltage bus,
• an npn output transistor having its base connected to the emitter of said pnp input transistor, its emitter connected to said output terminal and its collector connected to receive a current to supply to said output terminal during a track mode,
• a pnp output transistor having its base connected to the emitter of said npn input transistor, its emitter connected to said output terminal and its collector connected to transmit a current received from said output terminal during a track mode, and
• a control circuit connected to divert current from said bias current sources away from said input transistors during a hold mode.

A balanced control circuit for providing alternating circuit connections in response to alternating control signals, comprising:

• a first pair of differentially connected bipolar transistors of a common type that is either type-npn or type-pnp,
• a second pair of differentially connected bipolar transistors of a common type that is opposite to that of the first differential pair,
• respective output circuits connected to the transistors of said second differential pair for generating an alternating pair of bias signals in response to alternating control signals applied to the transistors of said second differential pair, and
• means for applying said bias signals to alternately actuate and deactuate the transistors of said first differential pair.